From cc61c1fede7d02cb8133ab0952ca3f3ba1f7fbb1 Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Tue, 12 Jul 2005 18:35:38 +0000 Subject: [PATCH] MIPS R2 instruction hazard handling. Signed-off-by: Ralf Baechle --- arch/mips/mm/c-r4k.c | 1 + include/asm-mips/hazards.h | 16 ++++++++++++++++ 2 files changed, 17 insertions(+) diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c index b90147399ea..08d7229a068 100644 --- a/arch/mips/mm/c-r4k.c +++ b/arch/mips/mm/c-r4k.c @@ -529,6 +529,7 @@ static void r4k_flush_icache_range(unsigned long __user start, args.end = end; on_each_cpu(local_r4k_flush_icache_range, &args, 1, 1); + instruction_hazard(); } /* diff --git a/include/asm-mips/hazards.h b/include/asm-mips/hazards.h index 181f08de889..f63d824e6e4 100644 --- a/include/asm-mips/hazards.h +++ b/include/asm-mips/hazards.h @@ -228,6 +228,22 @@ __asm__( #endif +#if defined(CONFIG_CPU_MIPS32_R2) || defined (CONFIG_CPU_MIPS64_R2) +#define instruction_hazard() \ +do { \ +__label__ __next; \ + __asm__ __volatile__( \ + " jr.hb %0 \n" \ + : \ + : "r" (&&__next)); \ +__next: \ + ; \ +} while (0) + +#else +#define instruction_hazard() do { } while (0) +#endif + #endif /* __ASSEMBLY__ */ #endif /* _ASM_HAZARDS_H */ -- 2.20.1