From ca590c1c45d1d06f842a82f6a591b94af95952b0 Mon Sep 17 00:00:00 2001 From: Dharageswari R Date: Thu, 6 Oct 2016 08:51:21 +0530 Subject: [PATCH] ASoC: Intel: Skylake: Use DPIB to update position for Playback stream DPIB is read currently from a buffer position in memory (indicated by the registers DPIB[U|L]BASE).Driver reads the position buffer on BDL completion interrupts to report the DMA position. But the BDL completion interrupt only indicates the last DMA transfer of the buffer is completed at the Intel HD Audio subsystem boundary. The periodic DMA Position-in-Buffer writes may be scheduled at the same time or later than the MSI and does not guarantee to reflect the position of the last buffer that was transferred. Whereas DPIB register in HDA space(vendor specific register indicated by SDxDPIB) reflects the actual data that is transferred. Hence update the position based on DPIB for playback. Signed-off-by: Dharageswari R Signed-off-by: Jeeja KP Signed-off-by: Mark Brown --- sound/soc/intel/skylake/skl-pcm.c | 18 ++++++++++++++++-- 1 file changed, 16 insertions(+), 2 deletions(-) diff --git a/sound/soc/intel/skylake/skl-pcm.c b/sound/soc/intel/skylake/skl-pcm.c index 58c728662600..c966b40da180 100644 --- a/sound/soc/intel/skylake/skl-pcm.c +++ b/sound/soc/intel/skylake/skl-pcm.c @@ -1031,10 +1031,24 @@ static snd_pcm_uframes_t skl_platform_pcm_pointer (struct snd_pcm_substream *substream) { struct hdac_ext_stream *hstream = get_hdac_ext_stream(substream); + struct hdac_ext_bus *ebus = get_bus_ctx(substream); unsigned int pos; - /* use the position buffer as default */ - pos = snd_hdac_stream_get_pos_posbuf(hdac_stream(hstream)); + /* + * Use DPIB for Playback stream as the periodic DMA Position-in- + * Buffer Writes may be scheduled at the same time or later than + * the MSI and does not guarantee to reflect the Position of the + * last buffer that was transferred. Whereas DPIB register in + * HAD space reflects the actual data that is transferred. + * Use the position buffer for capture, as DPIB write gets + * completed earlier than the actual data written to the DDR. + */ + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) + pos = readl(ebus->bus.remap_addr + AZX_REG_VS_SDXDPIB_XBASE + + (AZX_REG_VS_SDXDPIB_XINTERVAL * + hdac_stream(hstream)->index)); + else + pos = snd_hdac_stream_get_pos_posbuf(hdac_stream(hstream)); if (pos >= hdac_stream(hstream)->bufsize) pos = 0; -- 2.20.1