From ca291363ccc7c0e9b337fe3b46f732247238537e Mon Sep 17 00:00:00 2001 From: Paulo Zanoni Date: Wed, 6 Mar 2013 20:03:14 -0300 Subject: [PATCH] drm/i915: there's no DSPADDR register on Haswell So don't read it when we hang the GPU. This solves "unclaimed register" messages. Signed-off-by: Paulo Zanoni Reviewed-by: Ben Widawsky [danvet: Future-proof by adding a gen >= 7 check in addition to the !IS_HSW check from Paulo's original patch, suggested by Ben.] Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_display.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 1e706769de66..630a96770043 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -9349,7 +9349,8 @@ intel_display_capture_error_state(struct drm_device *dev) if (INTEL_INFO(dev)->gen <= 3) error->plane[i].size = I915_READ(DSPSIZE(i)); error->plane[i].pos = I915_READ(DSPPOS(i)); - error->plane[i].addr = I915_READ(DSPADDR(i)); + if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) + error->plane[i].addr = I915_READ(DSPADDR(i)); if (INTEL_INFO(dev)->gen >= 4) { error->plane[i].surface = I915_READ(DSPSURF(i)); error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i)); @@ -9394,7 +9395,8 @@ intel_display_print_error_state(struct seq_file *m, if (INTEL_INFO(dev)->gen <= 3) seq_printf(m, " SIZE: %08x\n", error->plane[i].size); seq_printf(m, " POS: %08x\n", error->plane[i].pos); - seq_printf(m, " ADDR: %08x\n", error->plane[i].addr); + if (!IS_HASWELL(dev)) + seq_printf(m, " ADDR: %08x\n", error->plane[i].addr); if (INTEL_INFO(dev)->gen >= 4) { seq_printf(m, " SURF: %08x\n", error->plane[i].surface); seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset); -- 2.20.1