From c97f8c922ea78195aa7d833d639d2963cc11af8e Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Sun, 19 Aug 2012 16:03:00 +1000 Subject: [PATCH] drm/nouveau/fifo: use defines instead of hardcoded class ids Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/core/engine/fifo/nv04.c | 2 +- drivers/gpu/drm/nouveau/core/engine/fifo/nv10.c | 2 +- drivers/gpu/drm/nouveau/core/engine/fifo/nv17.c | 2 +- drivers/gpu/drm/nouveau/core/engine/fifo/nv40.c | 2 +- drivers/gpu/drm/nouveau/core/engine/fifo/nv50.c | 4 ++-- drivers/gpu/drm/nouveau/core/engine/fifo/nv84.c | 4 ++-- drivers/gpu/drm/nouveau/core/engine/fifo/nvc0.c | 2 +- drivers/gpu/drm/nouveau/core/engine/fifo/nve0.c | 2 +- drivers/gpu/drm/nouveau/nouveau_chan.c | 12 ++++++++++-- 9 files changed, 20 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/nouveau/core/engine/fifo/nv04.c b/drivers/gpu/drm/nouveau/core/engine/fifo/nv04.c index cc49284be181..ea76e3e8c9c2 100644 --- a/drivers/gpu/drm/nouveau/core/engine/fifo/nv04.c +++ b/drivers/gpu/drm/nouveau/core/engine/fifo/nv04.c @@ -247,7 +247,7 @@ nv04_fifo_ofuncs = { static struct nouveau_oclass nv04_fifo_sclass[] = { - { 0x006b, &nv04_fifo_ofuncs }, + { NV03_CHANNEL_DMA_CLASS, &nv04_fifo_ofuncs }, {} }; diff --git a/drivers/gpu/drm/nouveau/core/engine/fifo/nv10.c b/drivers/gpu/drm/nouveau/core/engine/fifo/nv10.c index c4c78d50b396..4ba75422b89d 100644 --- a/drivers/gpu/drm/nouveau/core/engine/fifo/nv10.c +++ b/drivers/gpu/drm/nouveau/core/engine/fifo/nv10.c @@ -106,7 +106,7 @@ nv10_fifo_ofuncs = { static struct nouveau_oclass nv10_fifo_sclass[] = { - { 0x006e, &nv10_fifo_ofuncs }, + { NV10_CHANNEL_DMA_CLASS, &nv10_fifo_ofuncs }, {} }; diff --git a/drivers/gpu/drm/nouveau/core/engine/fifo/nv17.c b/drivers/gpu/drm/nouveau/core/engine/fifo/nv17.c index 1733765e8bf2..b96e6b0ae2b1 100644 --- a/drivers/gpu/drm/nouveau/core/engine/fifo/nv17.c +++ b/drivers/gpu/drm/nouveau/core/engine/fifo/nv17.c @@ -113,7 +113,7 @@ nv17_fifo_ofuncs = { static struct nouveau_oclass nv17_fifo_sclass[] = { - { 0x176e, &nv17_fifo_ofuncs }, + { NV17_CHANNEL_DMA_CLASS, &nv17_fifo_ofuncs }, {} }; diff --git a/drivers/gpu/drm/nouveau/core/engine/fifo/nv40.c b/drivers/gpu/drm/nouveau/core/engine/fifo/nv40.c index aef8ca106ac0..559c3b4e1b86 100644 --- a/drivers/gpu/drm/nouveau/core/engine/fifo/nv40.c +++ b/drivers/gpu/drm/nouveau/core/engine/fifo/nv40.c @@ -232,7 +232,7 @@ nv40_fifo_ofuncs = { static struct nouveau_oclass nv40_fifo_sclass[] = { - { 0x406e, &nv40_fifo_ofuncs }, + { NV40_CHANNEL_DMA_CLASS, &nv40_fifo_ofuncs }, {} }; diff --git a/drivers/gpu/drm/nouveau/core/engine/fifo/nv50.c b/drivers/gpu/drm/nouveau/core/engine/fifo/nv50.c index 44a0dce07e19..536e7634a00d 100644 --- a/drivers/gpu/drm/nouveau/core/engine/fifo/nv50.c +++ b/drivers/gpu/drm/nouveau/core/engine/fifo/nv50.c @@ -346,8 +346,8 @@ nv50_fifo_ofuncs_ind = { static struct nouveau_oclass nv50_fifo_sclass[] = { - { 0x506e, &nv50_fifo_ofuncs_dma }, - { 0x506f, &nv50_fifo_ofuncs_ind }, + { NV50_CHANNEL_DMA_CLASS, &nv50_fifo_ofuncs_dma }, + { NV50_CHANNEL_IND_CLASS, &nv50_fifo_ofuncs_ind }, {} }; diff --git a/drivers/gpu/drm/nouveau/core/engine/fifo/nv84.c b/drivers/gpu/drm/nouveau/core/engine/fifo/nv84.c index 88ca9e89a87a..55620fbd5c21 100644 --- a/drivers/gpu/drm/nouveau/core/engine/fifo/nv84.c +++ b/drivers/gpu/drm/nouveau/core/engine/fifo/nv84.c @@ -310,8 +310,8 @@ nv84_fifo_ofuncs_ind = { static struct nouveau_oclass nv84_fifo_sclass[] = { - { 0x826e, &nv84_fifo_ofuncs_dma }, - { 0x826f, &nv84_fifo_ofuncs_ind }, + { NV84_CHANNEL_DMA_CLASS, &nv84_fifo_ofuncs_dma }, + { NV84_CHANNEL_IND_CLASS, &nv84_fifo_ofuncs_ind }, {} }; diff --git a/drivers/gpu/drm/nouveau/core/engine/fifo/nvc0.c b/drivers/gpu/drm/nouveau/core/engine/fifo/nvc0.c index d10dca237ca3..dda0a442453e 100644 --- a/drivers/gpu/drm/nouveau/core/engine/fifo/nvc0.c +++ b/drivers/gpu/drm/nouveau/core/engine/fifo/nvc0.c @@ -258,7 +258,7 @@ nvc0_fifo_ofuncs = { static struct nouveau_oclass nvc0_fifo_sclass[] = { - { 0x906f, &nvc0_fifo_ofuncs }, + { NVC0_CHANNEL_IND_CLASS, &nvc0_fifo_ofuncs }, {} }; diff --git a/drivers/gpu/drm/nouveau/core/engine/fifo/nve0.c b/drivers/gpu/drm/nouveau/core/engine/fifo/nve0.c index 042afadbdf2e..f4803239c5f9 100644 --- a/drivers/gpu/drm/nouveau/core/engine/fifo/nve0.c +++ b/drivers/gpu/drm/nouveau/core/engine/fifo/nve0.c @@ -303,7 +303,7 @@ nve0_fifo_ofuncs = { static struct nouveau_oclass nve0_fifo_sclass[] = { - { 0xa06f, &nve0_fifo_ofuncs }, + { NVE0_CHANNEL_IND_CLASS, &nve0_fifo_ofuncs }, {} }; diff --git a/drivers/gpu/drm/nouveau/nouveau_chan.c b/drivers/gpu/drm/nouveau/nouveau_chan.c index e6451847df4a..55dc51c1b92e 100644 --- a/drivers/gpu/drm/nouveau/nouveau_chan.c +++ b/drivers/gpu/drm/nouveau/nouveau_chan.c @@ -187,7 +187,11 @@ nouveau_channel_ind(struct nouveau_drm *drm, struct nouveau_cli *cli, u32 parent, u32 handle, u32 engine, struct nouveau_channel **pchan) { - static const u16 oclasses[] = { 0xa06f, 0x906f, 0x826f, 0x506f, 0 }; + static const u16 oclasses[] = { NVE0_CHANNEL_IND_CLASS, + NVC0_CHANNEL_IND_CLASS, + NV84_CHANNEL_IND_CLASS, + NV50_CHANNEL_IND_CLASS, + 0 }; const u16 *oclass = oclasses; struct nve0_channel_ind_class args; struct nouveau_channel *chan; @@ -221,7 +225,11 @@ static int nouveau_channel_dma(struct nouveau_drm *drm, struct nouveau_cli *cli, u32 parent, u32 handle, struct nouveau_channel **pchan) { - static const u16 oclasses[] = { 0x406e, 0x176e, 0x006e, 0x006b, 0 }; + static const u16 oclasses[] = { NV40_CHANNEL_DMA_CLASS, + NV17_CHANNEL_DMA_CLASS, + NV10_CHANNEL_DMA_CLASS, + NV03_CHANNEL_DMA_CLASS, + 0 }; const u16 *oclass = oclasses; struct nv03_channel_dma_class args; struct nouveau_channel *chan; -- 2.20.1