From be929999fd706b1dc1eaf219fb9bd7fd65f384b1 Mon Sep 17 00:00:00 2001 From: Chanwoo Choi Date: Tue, 18 Mar 2014 06:25:58 +0900 Subject: [PATCH] ARM: dts: Add PMU dt data to support PMU for exynos4x12 ARM CPU has its own performance profiling unit(PMU, Perforamnce Monitoring Unit). This patch add PMU dt data to support PMU which count cache hit and miss events. PMU interrput list of Exynos4212 - <2 2> : INTG2[2] - PMUIRQ[0] for CPU0 - <3 2> : INTG3[2] - PMUIRQ[1] for CPU1 PMU interrput list of Exynos4412 - <2 2> : INTG2[2], PMUIRQ[0] for CPU0 - <3 2> : INTG3[2], PMUIRQ[1] for CPU1 - <18 2> : INTG18[2], PMUIRQ[2] : CPU2 - <19 2> : INTG19[2], PMUIRQ[3] : CPU3 Signed-off-by: Chanwoo Choi Signed-off-by: Kyungmin Park Reviewed-by: Tomasz Figa Signed-off-by: Kukjin Kim --- arch/arm/boot/dts/exynos4x12.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/boot/dts/exynos4x12.dtsi b/arch/arm/boot/dts/exynos4x12.dtsi index eec1e304435e..a1e76ec60e0a 100644 --- a/arch/arm/boot/dts/exynos4x12.dtsi +++ b/arch/arm/boot/dts/exynos4x12.dtsi @@ -31,6 +31,12 @@ mshc0 = &mshc_0; }; + pmu { + compatible = "arm,cortex-a9-pmu"; + interrupt-parent = <&combiner>; + interrupts = <2 2>, <3 2>, <18 2>, <19 2>; + }; + pd_isp: isp-power-domain@10023CA0 { compatible = "samsung,exynos4210-pd"; reg = <0x10023CA0 0x20>; -- 2.20.1