From bd6c5cab95a4f112af9ff1d8635b0cd5b6d8aafb Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Wed, 14 Jan 2015 15:22:32 +1000 Subject: [PATCH] drm/nouveau/ce: namespace + nvidia gpu names (no binary change) The namespace of NVKM is being changed to nvkm_ instead of nouveau_, which will be used for the DRM part of the driver. This is being done in order to make it very clear as to what part of the driver a given symbol belongs to, and as a minor step towards splitting the DRM driver out to be able to stand on its own (for virt). Because there's already a large amount of churn here anyway, this is as good a time as any to also switch to NVIDIA's device and chipset naming to ease collaboration with them. A comparison of objdump disassemblies proves no code changes. Signed-off-by: Ben Skeggs --- .../gpu/drm/nouveau/include/nvkm/engine/ce.h | 15 +- drivers/gpu/drm/nouveau/nvkm/engine/ce/Kbuild | 6 +- .../drm/nouveau/nvkm/engine/ce/fuc/com.fuc | 33 ++-- .../engine/ce/fuc/{nva3.fuc3 => gf100.fuc3} | 2 +- .../ce/fuc/{nvc0.fuc3.h => gf100.fuc3.h} | 4 +- .../engine/ce/fuc/{nvc0.fuc3 => gt215.fuc3} | 2 +- .../ce/fuc/{nva3.fuc3.h => gt215.fuc3.h} | 4 +- .../gpu/drm/nouveau/nvkm/engine/ce/gf100.c | 166 +++++++++++++++++ .../nvkm/engine/ce/{nve0.c => gk104.c} | 137 +++++++------- .../nvkm/engine/ce/{nva3.c => gt215.c} | 103 +++++------ drivers/gpu/drm/nouveau/nvkm/engine/ce/nvc0.c | 172 ------------------ .../drm/nouveau/nvkm/engine/device/gm100.c | 6 +- .../gpu/drm/nouveau/nvkm/engine/device/nv50.c | 8 +- .../gpu/drm/nouveau/nvkm/engine/device/nvc0.c | 26 +-- .../gpu/drm/nouveau/nvkm/engine/device/nve0.c | 44 ++--- 15 files changed, 353 insertions(+), 375 deletions(-) rename drivers/gpu/drm/nouveau/nvkm/engine/ce/fuc/{nva3.fuc3 => gf100.fuc3} (57%) rename drivers/gpu/drm/nouveau/nvkm/engine/ce/fuc/{nvc0.fuc3.h => gf100.fuc3.h} (99%) rename drivers/gpu/drm/nouveau/nvkm/engine/ce/fuc/{nvc0.fuc3 => gt215.fuc3} (57%) rename drivers/gpu/drm/nouveau/nvkm/engine/ce/fuc/{nva3.fuc3.h => gt215.fuc3.h} (99%) create mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/ce/gf100.c rename drivers/gpu/drm/nouveau/nvkm/engine/ce/{nve0.c => gk104.c} (51%) rename drivers/gpu/drm/nouveau/nvkm/engine/ce/{nva3.c => gt215.c} (60%) delete mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/ce/nvc0.c diff --git a/drivers/gpu/drm/nouveau/include/nvkm/engine/ce.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/ce.h index 92cfcf5ae9d4..7e29c52617ea 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/engine/ce.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/engine/ce.h @@ -2,13 +2,12 @@ #define __NVKM_CE_H__ #include -void nva3_ce_intr(struct nouveau_subdev *); - -extern struct nouveau_oclass nva3_ce_oclass; -extern struct nouveau_oclass nvc0_ce0_oclass; -extern struct nouveau_oclass nvc0_ce1_oclass; -extern struct nouveau_oclass nve0_ce0_oclass; -extern struct nouveau_oclass nve0_ce1_oclass; -extern struct nouveau_oclass nve0_ce2_oclass; +void gt215_ce_intr(struct nvkm_subdev *); +extern struct nvkm_oclass gt215_ce_oclass; +extern struct nvkm_oclass gf100_ce0_oclass; +extern struct nvkm_oclass gf100_ce1_oclass; +extern struct nvkm_oclass gk104_ce0_oclass; +extern struct nvkm_oclass gk104_ce1_oclass; +extern struct nvkm_oclass gk104_ce2_oclass; #endif diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/ce/Kbuild b/drivers/gpu/drm/nouveau/nvkm/engine/ce/Kbuild index 834523d8420f..858797453e0b 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/ce/Kbuild +++ b/drivers/gpu/drm/nouveau/nvkm/engine/ce/Kbuild @@ -1,3 +1,3 @@ -nvkm-y += nvkm/engine/ce/nva3.o -nvkm-y += nvkm/engine/ce/nvc0.o -nvkm-y += nvkm/engine/ce/nve0.o +nvkm-y += nvkm/engine/ce/gt215.o +nvkm-y += nvkm/engine/ce/gf100.o +nvkm-y += nvkm/engine/ce/gk104.o diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/ce/fuc/com.fuc b/drivers/gpu/drm/nouveau/nvkm/engine/ce/fuc/com.fuc index fcc4ba172443..a558dfa4d76a 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/ce/fuc/com.fuc +++ b/drivers/gpu/drm/nouveau/nvkm/engine/ce/fuc/com.fuc @@ -1,4 +1,4 @@ -/* fuc microcode for copy engine on nva3- chipsets +/* fuc microcode for copy engine on gt215- chipsets * * Copyright 2011 Red Hat Inc. * @@ -23,21 +23,14 @@ * Authors: Ben Skeggs */ -/* To build for nva3:nvc0 - * m4 -DNVA3 nva3_copy.fuc | envyas -a -w -m fuc -V nva3 -o nva3_copy.fuc.h - * - * To build for nvc0- - * m4 -DNVC0 nva3_copy.fuc | envyas -a -w -m fuc -V nva3 -o nvc0_copy.fuc.h - */ - -#ifdef NVA3 -.section #nva3_pce_data +#ifdef GT215 +.section #gt215_pce_data #else -.section #nvc0_pce_data +.section #gf100_pce_data #endif ctx_object: .b32 0 -#ifdef NVA3 +#ifdef GT215 ctx_dma: ctx_dma_query: .b32 0 ctx_dma_src: .b32 0 @@ -86,7 +79,7 @@ dispatch_table: // mthd 0x0140, PM_TRIGGER .b16 0x050 1 .b32 0x00010000 + #cmd_pm_trigger ~0xffffffff -#ifdef NVA3 +#ifdef GT215 // mthd 0x0180-0x018c, DMA_ .b16 0x060 #ctx_dma_count dispatch_dma: @@ -134,10 +127,10 @@ dispatch_dma: .b32 #ctx_query_counter ~0xffffffff .b16 0x800 0 -#ifdef NVA3 -.section #nva3_pce_code +#ifdef GT215 +.section #gt215_pce_code #else -.section #nvc0_pce_code +.section #gf100_pce_code #endif main: @@ -190,7 +183,7 @@ ih: swctx: mov $r4 0x7700 mov $xtargets $r4 -#ifdef NVA3 +#ifdef GT215 // target 7 hardcoded to ctx dma object mov $xdbase $r0 #else @@ -271,7 +264,7 @@ chsw: bra e #chsw_finish_load bset $flags $p1 call #swctx -#ifdef NVA3 +#ifdef GT215 // load dma objects back into TARGET regs mov $r5 #ctx_dma mov $r6 #ctx_dma_count @@ -396,7 +389,7 @@ cmd_pm_trigger: iowr I[$r2] $r3 ret -#ifdef NVA3 +#ifdef GT215 // SET_DMA_* method handler // // Inputs: @@ -547,7 +540,7 @@ cmd_exec_set_surface_tiled: ld b32 $r7 D[$r5 + #ctx_src_tile_mode] extr $r9 $r7 8:11 extr $r8 $r7 4:7 -#ifdef NVA3 +#ifdef GT215 add b32 $r8 2 #else add b32 $r8 3 diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/ce/fuc/nva3.fuc3 b/drivers/gpu/drm/nouveau/nvkm/engine/ce/fuc/gf100.fuc3 similarity index 57% rename from drivers/gpu/drm/nouveau/nvkm/engine/ce/fuc/nva3.fuc3 rename to drivers/gpu/drm/nouveau/nvkm/engine/ce/fuc/gf100.fuc3 index e670620227e7..36f0a99ac7a2 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/ce/fuc/nva3.fuc3 +++ b/drivers/gpu/drm/nouveau/nvkm/engine/ce/fuc/gf100.fuc3 @@ -1,2 +1,2 @@ -#define NVA3 +#define GF100 #include "com.fuc" diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/ce/fuc/nvc0.fuc3.h b/drivers/gpu/drm/nouveau/nvkm/engine/ce/fuc/gf100.fuc3.h similarity index 99% rename from drivers/gpu/drm/nouveau/nvkm/engine/ce/fuc/nvc0.fuc3.h rename to drivers/gpu/drm/nouveau/nvkm/engine/ce/fuc/gf100.fuc3.h index 042257daef8b..d9af6e4e4585 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/ce/fuc/nvc0.fuc3.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/ce/fuc/gf100.fuc3.h @@ -1,4 +1,4 @@ -uint32_t nvc0_pce_data[] = { +uint32_t gf100_pce_data[] = { /* 0x0000: ctx_object */ 0x00000000, /* 0x0004: ctx_query_address_high */ @@ -171,7 +171,7 @@ uint32_t nvc0_pce_data[] = { 0x00000800, }; -uint32_t nvc0_pce_code[] = { +uint32_t gf100_pce_code[] = { /* 0x0000: main */ 0x04fe04bd, 0x3517f000, diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/ce/fuc/nvc0.fuc3 b/drivers/gpu/drm/nouveau/nvkm/engine/ce/fuc/gt215.fuc3 similarity index 57% rename from drivers/gpu/drm/nouveau/nvkm/engine/ce/fuc/nvc0.fuc3 rename to drivers/gpu/drm/nouveau/nvkm/engine/ce/fuc/gt215.fuc3 index df6866c34e16..07bda93cfd79 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/ce/fuc/nvc0.fuc3 +++ b/drivers/gpu/drm/nouveau/nvkm/engine/ce/fuc/gt215.fuc3 @@ -1,2 +1,2 @@ -#define NVC0 +#define GT215 #include "com.fuc" diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/ce/fuc/nva3.fuc3.h b/drivers/gpu/drm/nouveau/nvkm/engine/ce/fuc/gt215.fuc3.h similarity index 99% rename from drivers/gpu/drm/nouveau/nvkm/engine/ce/fuc/nva3.fuc3.h rename to drivers/gpu/drm/nouveau/nvkm/engine/ce/fuc/gt215.fuc3.h index 362872df592a..f42c0d0d6cee 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/ce/fuc/nva3.fuc3.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/ce/fuc/gt215.fuc3.h @@ -1,4 +1,4 @@ -uint32_t nva3_pce_data[] = { +uint32_t gt215_pce_data[] = { /* 0x0000: ctx_object */ 0x00000000, /* 0x0004: ctx_dma */ @@ -183,7 +183,7 @@ uint32_t nva3_pce_data[] = { 0x00000800, }; -uint32_t nva3_pce_code[] = { +uint32_t gt215_pce_code[] = { /* 0x0000: main */ 0x04fe04bd, 0x3517f000, diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/ce/gf100.c b/drivers/gpu/drm/nouveau/nvkm/engine/ce/gf100.c new file mode 100644 index 000000000000..2d2e549c2e34 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/ce/gf100.c @@ -0,0 +1,166 @@ +/* + * Copyright 2012 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Ben Skeggs + */ +#include +#include +#include "fuc/gf100.fuc3.h" + +struct gf100_ce_priv { + struct nvkm_falcon base; +}; + +/******************************************************************************* + * Copy object classes + ******************************************************************************/ + +static struct nvkm_oclass +gf100_ce0_sclass[] = { + { 0x90b5, &nvkm_object_ofuncs }, + {}, +}; + +static struct nvkm_oclass +gf100_ce1_sclass[] = { + { 0x90b8, &nvkm_object_ofuncs }, + {}, +}; + +/******************************************************************************* + * PCE context + ******************************************************************************/ + +static struct nvkm_ofuncs +gf100_ce_context_ofuncs = { + .ctor = _nvkm_falcon_context_ctor, + .dtor = _nvkm_falcon_context_dtor, + .init = _nvkm_falcon_context_init, + .fini = _nvkm_falcon_context_fini, + .rd32 = _nvkm_falcon_context_rd32, + .wr32 = _nvkm_falcon_context_wr32, +}; + +static struct nvkm_oclass +gf100_ce0_cclass = { + .handle = NV_ENGCTX(CE0, 0xc0), + .ofuncs = &gf100_ce_context_ofuncs, +}; + +static struct nvkm_oclass +gf100_ce1_cclass = { + .handle = NV_ENGCTX(CE1, 0xc0), + .ofuncs = &gf100_ce_context_ofuncs, +}; + +/******************************************************************************* + * PCE engine/subdev functions + ******************************************************************************/ + +static int +gf100_ce_init(struct nvkm_object *object) +{ + struct gf100_ce_priv *priv = (void *)object; + int ret; + + ret = nvkm_falcon_init(&priv->base); + if (ret) + return ret; + + nv_wo32(priv, 0x084, nv_engidx(&priv->base.base) - NVDEV_ENGINE_CE0); + return 0; +} + +static int +gf100_ce0_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) +{ + struct gf100_ce_priv *priv; + int ret; + + ret = nvkm_falcon_create(parent, engine, oclass, 0x104000, true, + "PCE0", "ce0", &priv); + *pobject = nv_object(priv); + if (ret) + return ret; + + nv_subdev(priv)->unit = 0x00000040; + nv_subdev(priv)->intr = gt215_ce_intr; + nv_engine(priv)->cclass = &gf100_ce0_cclass; + nv_engine(priv)->sclass = gf100_ce0_sclass; + nv_falcon(priv)->code.data = gf100_pce_code; + nv_falcon(priv)->code.size = sizeof(gf100_pce_code); + nv_falcon(priv)->data.data = gf100_pce_data; + nv_falcon(priv)->data.size = sizeof(gf100_pce_data); + return 0; +} + +static int +gf100_ce1_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) +{ + struct gf100_ce_priv *priv; + int ret; + + ret = nvkm_falcon_create(parent, engine, oclass, 0x105000, true, + "PCE1", "ce1", &priv); + *pobject = nv_object(priv); + if (ret) + return ret; + + nv_subdev(priv)->unit = 0x00000080; + nv_subdev(priv)->intr = gt215_ce_intr; + nv_engine(priv)->cclass = &gf100_ce1_cclass; + nv_engine(priv)->sclass = gf100_ce1_sclass; + nv_falcon(priv)->code.data = gf100_pce_code; + nv_falcon(priv)->code.size = sizeof(gf100_pce_code); + nv_falcon(priv)->data.data = gf100_pce_data; + nv_falcon(priv)->data.size = sizeof(gf100_pce_data); + return 0; +} + +struct nvkm_oclass +gf100_ce0_oclass = { + .handle = NV_ENGINE(CE0, 0xc0), + .ofuncs = &(struct nvkm_ofuncs) { + .ctor = gf100_ce0_ctor, + .dtor = _nvkm_falcon_dtor, + .init = gf100_ce_init, + .fini = _nvkm_falcon_fini, + .rd32 = _nvkm_falcon_rd32, + .wr32 = _nvkm_falcon_wr32, + }, +}; + +struct nvkm_oclass +gf100_ce1_oclass = { + .handle = NV_ENGINE(CE1, 0xc0), + .ofuncs = &(struct nvkm_ofuncs) { + .ctor = gf100_ce1_ctor, + .dtor = _nvkm_falcon_dtor, + .init = gf100_ce_init, + .fini = _nvkm_falcon_fini, + .rd32 = _nvkm_falcon_rd32, + .wr32 = _nvkm_falcon_wr32, + }, +}; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/ce/nve0.c b/drivers/gpu/drm/nouveau/nvkm/engine/ce/gk104.c similarity index 51% rename from drivers/gpu/drm/nouveau/nvkm/engine/ce/nve0.c rename to drivers/gpu/drm/nouveau/nvkm/engine/ce/gk104.c index b2b31d1b768c..a998932fae45 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/ce/nve0.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/ce/gk104.c @@ -21,24 +21,21 @@ * * Authors: Ben Skeggs */ +#include -#include -#include #include -#include - -struct nve0_ce_priv { - struct nouveau_engine base; +struct gk104_ce_priv { + struct nvkm_engine base; }; /******************************************************************************* * Copy object classes ******************************************************************************/ -static struct nouveau_oclass -nve0_ce_sclass[] = { - { 0xa0b5, &nouveau_object_ofuncs }, +static struct nvkm_oclass +gk104_ce_sclass[] = { + { 0xa0b5, &nvkm_object_ofuncs }, {}, }; @@ -46,20 +43,20 @@ nve0_ce_sclass[] = { * PCE context ******************************************************************************/ -static struct nouveau_ofuncs -nve0_ce_context_ofuncs = { - .ctor = _nouveau_engctx_ctor, - .dtor = _nouveau_engctx_dtor, - .init = _nouveau_engctx_init, - .fini = _nouveau_engctx_fini, - .rd32 = _nouveau_engctx_rd32, - .wr32 = _nouveau_engctx_wr32, +static struct nvkm_ofuncs +gk104_ce_context_ofuncs = { + .ctor = _nvkm_engctx_ctor, + .dtor = _nvkm_engctx_dtor, + .init = _nvkm_engctx_init, + .fini = _nvkm_engctx_fini, + .rd32 = _nvkm_engctx_rd32, + .wr32 = _nvkm_engctx_wr32, }; -static struct nouveau_oclass -nve0_ce_cclass = { +static struct nvkm_oclass +gk104_ce_cclass = { .handle = NV_ENGCTX(CE0, 0xc0), - .ofuncs = &nve0_ce_context_ofuncs, + .ofuncs = &gk104_ce_context_ofuncs, }; /******************************************************************************* @@ -67,10 +64,10 @@ nve0_ce_cclass = { ******************************************************************************/ static void -nve0_ce_intr(struct nouveau_subdev *subdev) +gk104_ce_intr(struct nvkm_subdev *subdev) { const int ce = nv_subidx(subdev) - NVDEV_ENGINE_CE0; - struct nve0_ce_priv *priv = (void *)subdev; + struct gk104_ce_priv *priv = (void *)subdev; u32 stat = nv_rd32(priv, 0x104908 + (ce * 0x1000)); if (stat) { @@ -80,97 +77,97 @@ nve0_ce_intr(struct nouveau_subdev *subdev) } static int -nve0_ce0_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +gk104_ce0_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { - struct nve0_ce_priv *priv; + struct gk104_ce_priv *priv; int ret; - ret = nouveau_engine_create(parent, engine, oclass, true, - "PCE0", "ce0", &priv); + ret = nvkm_engine_create(parent, engine, oclass, true, + "PCE0", "ce0", &priv); *pobject = nv_object(priv); if (ret) return ret; nv_subdev(priv)->unit = 0x00000040; - nv_subdev(priv)->intr = nve0_ce_intr; - nv_engine(priv)->cclass = &nve0_ce_cclass; - nv_engine(priv)->sclass = nve0_ce_sclass; + nv_subdev(priv)->intr = gk104_ce_intr; + nv_engine(priv)->cclass = &gk104_ce_cclass; + nv_engine(priv)->sclass = gk104_ce_sclass; return 0; } static int -nve0_ce1_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +gk104_ce1_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { - struct nve0_ce_priv *priv; + struct gk104_ce_priv *priv; int ret; - ret = nouveau_engine_create(parent, engine, oclass, true, - "PCE1", "ce1", &priv); + ret = nvkm_engine_create(parent, engine, oclass, true, + "PCE1", "ce1", &priv); *pobject = nv_object(priv); if (ret) return ret; nv_subdev(priv)->unit = 0x00000080; - nv_subdev(priv)->intr = nve0_ce_intr; - nv_engine(priv)->cclass = &nve0_ce_cclass; - nv_engine(priv)->sclass = nve0_ce_sclass; + nv_subdev(priv)->intr = gk104_ce_intr; + nv_engine(priv)->cclass = &gk104_ce_cclass; + nv_engine(priv)->sclass = gk104_ce_sclass; return 0; } static int -nve0_ce2_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +gk104_ce2_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { - struct nve0_ce_priv *priv; + struct gk104_ce_priv *priv; int ret; - ret = nouveau_engine_create(parent, engine, oclass, true, - "PCE2", "ce2", &priv); + ret = nvkm_engine_create(parent, engine, oclass, true, + "PCE2", "ce2", &priv); *pobject = nv_object(priv); if (ret) return ret; nv_subdev(priv)->unit = 0x00200000; - nv_subdev(priv)->intr = nve0_ce_intr; - nv_engine(priv)->cclass = &nve0_ce_cclass; - nv_engine(priv)->sclass = nve0_ce_sclass; + nv_subdev(priv)->intr = gk104_ce_intr; + nv_engine(priv)->cclass = &gk104_ce_cclass; + nv_engine(priv)->sclass = gk104_ce_sclass; return 0; } -struct nouveau_oclass -nve0_ce0_oclass = { +struct nvkm_oclass +gk104_ce0_oclass = { .handle = NV_ENGINE(CE0, 0xe0), - .ofuncs = &(struct nouveau_ofuncs) { - .ctor = nve0_ce0_ctor, - .dtor = _nouveau_engine_dtor, - .init = _nouveau_engine_init, - .fini = _nouveau_engine_fini, + .ofuncs = &(struct nvkm_ofuncs) { + .ctor = gk104_ce0_ctor, + .dtor = _nvkm_engine_dtor, + .init = _nvkm_engine_init, + .fini = _nvkm_engine_fini, }, }; -struct nouveau_oclass -nve0_ce1_oclass = { +struct nvkm_oclass +gk104_ce1_oclass = { .handle = NV_ENGINE(CE1, 0xe0), - .ofuncs = &(struct nouveau_ofuncs) { - .ctor = nve0_ce1_ctor, - .dtor = _nouveau_engine_dtor, - .init = _nouveau_engine_init, - .fini = _nouveau_engine_fini, + .ofuncs = &(struct nvkm_ofuncs) { + .ctor = gk104_ce1_ctor, + .dtor = _nvkm_engine_dtor, + .init = _nvkm_engine_init, + .fini = _nvkm_engine_fini, }, }; -struct nouveau_oclass -nve0_ce2_oclass = { +struct nvkm_oclass +gk104_ce2_oclass = { .handle = NV_ENGINE(CE2, 0xe0), - .ofuncs = &(struct nouveau_ofuncs) { - .ctor = nve0_ce2_ctor, - .dtor = _nouveau_engine_dtor, - .init = _nouveau_engine_init, - .fini = _nouveau_engine_fini, + .ofuncs = &(struct nvkm_ofuncs) { + .ctor = gk104_ce2_ctor, + .dtor = _nvkm_engine_dtor, + .init = _nvkm_engine_init, + .fini = _nvkm_engine_fini, }, }; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/ce/nva3.c b/drivers/gpu/drm/nouveau/nvkm/engine/ce/gt215.c similarity index 60% rename from drivers/gpu/drm/nouveau/nvkm/engine/ce/nva3.c rename to drivers/gpu/drm/nouveau/nvkm/engine/ce/gt215.c index b14617ac5abe..d8bb4293bc11 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/ce/nva3.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/ce/gt215.c @@ -21,32 +21,26 @@ * * Authors: Ben Skeggs */ - +#include #include #include -#include - -#include -#include +#include "fuc/gt215.fuc3.h" #include #include #include - -#include "fuc/nva3.fuc3.h" - -struct nva3_ce_priv { - struct nouveau_falcon base; +struct gt215_ce_priv { + struct nvkm_falcon base; }; /******************************************************************************* * Copy object classes ******************************************************************************/ -static struct nouveau_oclass -nva3_ce_sclass[] = { - { 0x85b5, &nouveau_object_ofuncs }, +static struct nvkm_oclass +gt215_ce_sclass[] = { + { 0x85b5, &nvkm_object_ofuncs }, {} }; @@ -54,16 +48,16 @@ nva3_ce_sclass[] = { * PCE context ******************************************************************************/ -static struct nouveau_oclass -nva3_ce_cclass = { +static struct nvkm_oclass +gt215_ce_cclass = { .handle = NV_ENGCTX(CE0, 0xa3), - .ofuncs = &(struct nouveau_ofuncs) { - .ctor = _nouveau_falcon_context_ctor, - .dtor = _nouveau_falcon_context_dtor, - .init = _nouveau_falcon_context_init, - .fini = _nouveau_falcon_context_fini, - .rd32 = _nouveau_falcon_context_rd32, - .wr32 = _nouveau_falcon_context_wr32, + .ofuncs = &(struct nvkm_ofuncs) { + .ctor = _nvkm_falcon_context_ctor, + .dtor = _nvkm_falcon_context_dtor, + .init = _nvkm_falcon_context_init, + .fini = _nvkm_falcon_context_fini, + .rd32 = _nvkm_falcon_context_rd32, + .wr32 = _nvkm_falcon_context_wr32, }, }; @@ -72,7 +66,8 @@ nva3_ce_cclass = { * PCE engine/subdev functions ******************************************************************************/ -static const struct nouveau_enum nva3_ce_isr_error_name[] = { +static const struct nvkm_enum +gt215_ce_isr_error_name[] = { { 0x0001, "ILLEGAL_MTHD" }, { 0x0002, "INVALID_ENUM" }, { 0x0003, "INVALID_BITFIELD" }, @@ -80,12 +75,12 @@ static const struct nouveau_enum nva3_ce_isr_error_name[] = { }; void -nva3_ce_intr(struct nouveau_subdev *subdev) +gt215_ce_intr(struct nvkm_subdev *subdev) { - struct nouveau_fifo *pfifo = nouveau_fifo(subdev); - struct nouveau_engine *engine = nv_engine(subdev); - struct nouveau_falcon *falcon = (void *)subdev; - struct nouveau_object *engctx; + struct nvkm_fifo *pfifo = nvkm_fifo(subdev); + struct nvkm_engine *engine = nv_engine(subdev); + struct nvkm_falcon *falcon = (void *)subdev; + struct nvkm_object *engctx; u32 dispatch = nv_ro32(falcon, 0x01c); u32 stat = nv_ro32(falcon, 0x008) & dispatch & ~(dispatch >> 16); u64 inst = nv_ro32(falcon, 0x050) & 0x3fffffff; @@ -96,14 +91,14 @@ nva3_ce_intr(struct nouveau_subdev *subdev) u32 data = nv_ro32(falcon, 0x044); int chid; - engctx = nouveau_engctx_get(engine, inst); + engctx = nvkm_engctx_get(engine, inst); chid = pfifo->chid(pfifo, engctx); if (stat & 0x00000040) { nv_error(falcon, "DISPATCH_ERROR ["); - nouveau_enum_print(nva3_ce_isr_error_name, ssta); + nvkm_enum_print(gt215_ce_isr_error_name, ssta); pr_cont("] ch %d [0x%010llx %s] subc %d mthd 0x%04x data 0x%08x\n", - chid, inst << 12, nouveau_client_name(engctx), subc, + chid, inst << 12, nvkm_client_name(engctx), subc, mthd, data); nv_wo32(falcon, 0x004, 0x00000040); stat &= ~0x00000040; @@ -114,44 +109,44 @@ nva3_ce_intr(struct nouveau_subdev *subdev) nv_wo32(falcon, 0x004, stat); } - nouveau_engctx_put(engctx); + nvkm_engctx_put(engctx); } static int -nva3_ce_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +gt215_ce_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { bool enable = (nv_device(parent)->chipset != 0xaf); - struct nva3_ce_priv *priv; + struct gt215_ce_priv *priv; int ret; - ret = nouveau_falcon_create(parent, engine, oclass, 0x104000, enable, - "PCE0", "ce0", &priv); + ret = nvkm_falcon_create(parent, engine, oclass, 0x104000, enable, + "PCE0", "ce0", &priv); *pobject = nv_object(priv); if (ret) return ret; nv_subdev(priv)->unit = 0x00802000; - nv_subdev(priv)->intr = nva3_ce_intr; - nv_engine(priv)->cclass = &nva3_ce_cclass; - nv_engine(priv)->sclass = nva3_ce_sclass; - nv_falcon(priv)->code.data = nva3_pce_code; - nv_falcon(priv)->code.size = sizeof(nva3_pce_code); - nv_falcon(priv)->data.data = nva3_pce_data; - nv_falcon(priv)->data.size = sizeof(nva3_pce_data); + nv_subdev(priv)->intr = gt215_ce_intr; + nv_engine(priv)->cclass = >215_ce_cclass; + nv_engine(priv)->sclass = gt215_ce_sclass; + nv_falcon(priv)->code.data = gt215_pce_code; + nv_falcon(priv)->code.size = sizeof(gt215_pce_code); + nv_falcon(priv)->data.data = gt215_pce_data; + nv_falcon(priv)->data.size = sizeof(gt215_pce_data); return 0; } -struct nouveau_oclass -nva3_ce_oclass = { +struct nvkm_oclass +gt215_ce_oclass = { .handle = NV_ENGINE(CE0, 0xa3), - .ofuncs = &(struct nouveau_ofuncs) { - .ctor = nva3_ce_ctor, - .dtor = _nouveau_falcon_dtor, - .init = _nouveau_falcon_init, - .fini = _nouveau_falcon_fini, - .rd32 = _nouveau_falcon_rd32, - .wr32 = _nouveau_falcon_wr32, + .ofuncs = &(struct nvkm_ofuncs) { + .ctor = gt215_ce_ctor, + .dtor = _nvkm_falcon_dtor, + .init = _nvkm_falcon_init, + .fini = _nvkm_falcon_fini, + .rd32 = _nvkm_falcon_rd32, + .wr32 = _nvkm_falcon_wr32, }, }; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/ce/nvc0.c b/drivers/gpu/drm/nouveau/nvkm/engine/ce/nvc0.c deleted file mode 100644 index f5dff133362d..000000000000 --- a/drivers/gpu/drm/nouveau/nvkm/engine/ce/nvc0.c +++ /dev/null @@ -1,172 +0,0 @@ -/* - * Copyright 2012 Red Hat Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: Ben Skeggs - */ - -#include -#include -#include - -#include -#include - -#include "fuc/nvc0.fuc3.h" - -struct nvc0_ce_priv { - struct nouveau_falcon base; -}; - -/******************************************************************************* - * Copy object classes - ******************************************************************************/ - -static struct nouveau_oclass -nvc0_ce0_sclass[] = { - { 0x90b5, &nouveau_object_ofuncs }, - {}, -}; - -static struct nouveau_oclass -nvc0_ce1_sclass[] = { - { 0x90b8, &nouveau_object_ofuncs }, - {}, -}; - -/******************************************************************************* - * PCE context - ******************************************************************************/ - -static struct nouveau_ofuncs -nvc0_ce_context_ofuncs = { - .ctor = _nouveau_falcon_context_ctor, - .dtor = _nouveau_falcon_context_dtor, - .init = _nouveau_falcon_context_init, - .fini = _nouveau_falcon_context_fini, - .rd32 = _nouveau_falcon_context_rd32, - .wr32 = _nouveau_falcon_context_wr32, -}; - -static struct nouveau_oclass -nvc0_ce0_cclass = { - .handle = NV_ENGCTX(CE0, 0xc0), - .ofuncs = &nvc0_ce_context_ofuncs, -}; - -static struct nouveau_oclass -nvc0_ce1_cclass = { - .handle = NV_ENGCTX(CE1, 0xc0), - .ofuncs = &nvc0_ce_context_ofuncs, -}; - -/******************************************************************************* - * PCE engine/subdev functions - ******************************************************************************/ - -static int -nvc0_ce_init(struct nouveau_object *object) -{ - struct nvc0_ce_priv *priv = (void *)object; - int ret; - - ret = nouveau_falcon_init(&priv->base); - if (ret) - return ret; - - nv_wo32(priv, 0x084, nv_engidx(&priv->base.base) - NVDEV_ENGINE_CE0); - return 0; -} - -static int -nvc0_ce0_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) -{ - struct nvc0_ce_priv *priv; - int ret; - - ret = nouveau_falcon_create(parent, engine, oclass, 0x104000, true, - "PCE0", "ce0", &priv); - *pobject = nv_object(priv); - if (ret) - return ret; - - nv_subdev(priv)->unit = 0x00000040; - nv_subdev(priv)->intr = nva3_ce_intr; - nv_engine(priv)->cclass = &nvc0_ce0_cclass; - nv_engine(priv)->sclass = nvc0_ce0_sclass; - nv_falcon(priv)->code.data = nvc0_pce_code; - nv_falcon(priv)->code.size = sizeof(nvc0_pce_code); - nv_falcon(priv)->data.data = nvc0_pce_data; - nv_falcon(priv)->data.size = sizeof(nvc0_pce_data); - return 0; -} - -static int -nvc0_ce1_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) -{ - struct nvc0_ce_priv *priv; - int ret; - - ret = nouveau_falcon_create(parent, engine, oclass, 0x105000, true, - "PCE1", "ce1", &priv); - *pobject = nv_object(priv); - if (ret) - return ret; - - nv_subdev(priv)->unit = 0x00000080; - nv_subdev(priv)->intr = nva3_ce_intr; - nv_engine(priv)->cclass = &nvc0_ce1_cclass; - nv_engine(priv)->sclass = nvc0_ce1_sclass; - nv_falcon(priv)->code.data = nvc0_pce_code; - nv_falcon(priv)->code.size = sizeof(nvc0_pce_code); - nv_falcon(priv)->data.data = nvc0_pce_data; - nv_falcon(priv)->data.size = sizeof(nvc0_pce_data); - return 0; -} - -struct nouveau_oclass -nvc0_ce0_oclass = { - .handle = NV_ENGINE(CE0, 0xc0), - .ofuncs = &(struct nouveau_ofuncs) { - .ctor = nvc0_ce0_ctor, - .dtor = _nouveau_falcon_dtor, - .init = nvc0_ce_init, - .fini = _nouveau_falcon_fini, - .rd32 = _nouveau_falcon_rd32, - .wr32 = _nouveau_falcon_wr32, - }, -}; - -struct nouveau_oclass -nvc0_ce1_oclass = { - .handle = NV_ENGINE(CE1, 0xc0), - .ofuncs = &(struct nouveau_ofuncs) { - .ctor = nvc0_ce1_ctor, - .dtor = _nouveau_falcon_dtor, - .init = nvc0_ce_init, - .fini = _nouveau_falcon_fini, - .rd32 = _nouveau_falcon_rd32, - .wr32 = _nouveau_falcon_wr32, - }, -}; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c index 342305f8abd8..dfc9e544e3e6 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c @@ -88,11 +88,11 @@ gm100_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = gm107_gr_oclass; device->oclass[NVDEV_ENGINE_DISP ] = gm107_disp_oclass; - device->oclass[NVDEV_ENGINE_CE0 ] = &nve0_ce0_oclass; + device->oclass[NVDEV_ENGINE_CE0 ] = &gk104_ce0_oclass; #if 0 - device->oclass[NVDEV_ENGINE_CE1 ] = &nve0_ce1_oclass; + device->oclass[NVDEV_ENGINE_CE1 ] = &gk104_ce1_oclass; #endif - device->oclass[NVDEV_ENGINE_CE2 ] = &nve0_ce2_oclass; + device->oclass[NVDEV_ENGINE_CE2 ] = &gk104_ce2_oclass; #if 0 device->oclass[NVDEV_ENGINE_MSVLD ] = &nve0_msvld_oclass; device->oclass[NVDEV_ENGINE_MSPDEC ] = &nve0_mspdec_oclass; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c index b74e27bb81f8..88353d33974f 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c @@ -375,7 +375,7 @@ nv50_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_MSPDEC ] = &nv98_mspdec_oclass; device->oclass[NVDEV_ENGINE_MSVLD ] = &nv98_msvld_oclass; device->oclass[NVDEV_ENGINE_MSPPP ] = &nv98_msppp_oclass; - device->oclass[NVDEV_ENGINE_CE0 ] = &nva3_ce_oclass; + device->oclass[NVDEV_ENGINE_CE0 ] = >215_ce_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass; device->oclass[NVDEV_ENGINE_PM ] = nva3_pm_oclass; break; @@ -405,7 +405,7 @@ nv50_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_MSPDEC ] = &nv98_mspdec_oclass; device->oclass[NVDEV_ENGINE_MSVLD ] = &nv98_msvld_oclass; device->oclass[NVDEV_ENGINE_MSPPP ] = &nv98_msppp_oclass; - device->oclass[NVDEV_ENGINE_CE0 ] = &nva3_ce_oclass; + device->oclass[NVDEV_ENGINE_CE0 ] = >215_ce_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass; device->oclass[NVDEV_ENGINE_PM ] = nva3_pm_oclass; break; @@ -435,7 +435,7 @@ nv50_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_MSPDEC ] = &nv98_mspdec_oclass; device->oclass[NVDEV_ENGINE_MSVLD ] = &nv98_msvld_oclass; device->oclass[NVDEV_ENGINE_MSPPP ] = &nv98_msppp_oclass; - device->oclass[NVDEV_ENGINE_CE0 ] = &nva3_ce_oclass; + device->oclass[NVDEV_ENGINE_CE0 ] = >215_ce_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass; device->oclass[NVDEV_ENGINE_PM ] = nva3_pm_oclass; break; @@ -465,7 +465,7 @@ nv50_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_MSPDEC ] = &nv98_mspdec_oclass; device->oclass[NVDEV_ENGINE_MSVLD ] = &nv98_msvld_oclass; device->oclass[NVDEV_ENGINE_MSPPP ] = &nv98_msppp_oclass; - device->oclass[NVDEV_ENGINE_CE0 ] = &nva3_ce_oclass; + device->oclass[NVDEV_ENGINE_CE0 ] = >215_ce_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass; device->oclass[NVDEV_ENGINE_PM ] = nva3_pm_oclass; break; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c index a4859a541aea..fd87b8f955ed 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c @@ -87,8 +87,8 @@ nvc0_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_MSPDEC ] = &nvc0_mspdec_oclass; device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass; device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass; - device->oclass[NVDEV_ENGINE_CE0 ] = &nvc0_ce0_oclass; - device->oclass[NVDEV_ENGINE_CE1 ] = &nvc0_ce1_oclass; + device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass; + device->oclass[NVDEV_ENGINE_CE1 ] = &gf100_ce1_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass; device->oclass[NVDEV_ENGINE_PM ] = &nvc0_pm_oclass; break; @@ -120,8 +120,8 @@ nvc0_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_MSPDEC ] = &nvc0_mspdec_oclass; device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass; device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass; - device->oclass[NVDEV_ENGINE_CE0 ] = &nvc0_ce0_oclass; - device->oclass[NVDEV_ENGINE_CE1 ] = &nvc0_ce1_oclass; + device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass; + device->oclass[NVDEV_ENGINE_CE1 ] = &gf100_ce1_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass; device->oclass[NVDEV_ENGINE_PM ] = &nvc0_pm_oclass; break; @@ -153,7 +153,7 @@ nvc0_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_MSPDEC ] = &nvc0_mspdec_oclass; device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass; device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass; - device->oclass[NVDEV_ENGINE_CE0 ] = &nvc0_ce0_oclass; + device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass; device->oclass[NVDEV_ENGINE_PM ] = &nvc0_pm_oclass; break; @@ -185,8 +185,8 @@ nvc0_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_MSPDEC ] = &nvc0_mspdec_oclass; device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass; device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass; - device->oclass[NVDEV_ENGINE_CE0 ] = &nvc0_ce0_oclass; - device->oclass[NVDEV_ENGINE_CE1 ] = &nvc0_ce1_oclass; + device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass; + device->oclass[NVDEV_ENGINE_CE1 ] = &gf100_ce1_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass; device->oclass[NVDEV_ENGINE_PM ] = &nvc0_pm_oclass; break; @@ -218,7 +218,7 @@ nvc0_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_MSPDEC ] = &nvc0_mspdec_oclass; device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass; device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass; - device->oclass[NVDEV_ENGINE_CE0 ] = &nvc0_ce0_oclass; + device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass; device->oclass[NVDEV_ENGINE_PM ] = &nvc0_pm_oclass; break; @@ -250,7 +250,7 @@ nvc0_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_MSPDEC ] = &nvc0_mspdec_oclass; device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass; device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass; - device->oclass[NVDEV_ENGINE_CE0 ] = &nvc0_ce0_oclass; + device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass; device->oclass[NVDEV_ENGINE_PM ] = &nvc0_pm_oclass; break; @@ -282,8 +282,8 @@ nvc0_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_MSPDEC ] = &nvc0_mspdec_oclass; device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass; device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass; - device->oclass[NVDEV_ENGINE_CE0 ] = &nvc0_ce0_oclass; - device->oclass[NVDEV_ENGINE_CE1 ] = &nvc0_ce1_oclass; + device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass; + device->oclass[NVDEV_ENGINE_CE1 ] = &gf100_ce1_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass; device->oclass[NVDEV_ENGINE_PM ] = &nvc0_pm_oclass; break; @@ -315,7 +315,7 @@ nvc0_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_MSPDEC ] = &nvc0_mspdec_oclass; device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass; device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass; - device->oclass[NVDEV_ENGINE_CE0 ] = &nvc0_ce0_oclass; + device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nvd0_disp_oclass; device->oclass[NVDEV_ENGINE_PM ] = &nvc0_pm_oclass; break; @@ -345,7 +345,7 @@ nvc0_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_MSPDEC ] = &nvc0_mspdec_oclass; device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass; device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass; - device->oclass[NVDEV_ENGINE_CE0 ] = &nvc0_ce0_oclass; + device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nvd0_disp_oclass; device->oclass[NVDEV_ENGINE_PM ] = &nvc0_pm_oclass; break; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c index 962a810d2b83..76cc21d383cb 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c @@ -85,9 +85,9 @@ nve0_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = nve4_gr_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nve0_disp_oclass; - device->oclass[NVDEV_ENGINE_CE0 ] = &nve0_ce0_oclass; - device->oclass[NVDEV_ENGINE_CE1 ] = &nve0_ce1_oclass; - device->oclass[NVDEV_ENGINE_CE2 ] = &nve0_ce2_oclass; + device->oclass[NVDEV_ENGINE_CE0 ] = &gk104_ce0_oclass; + device->oclass[NVDEV_ENGINE_CE1 ] = &gk104_ce1_oclass; + device->oclass[NVDEV_ENGINE_CE2 ] = &gk104_ce2_oclass; device->oclass[NVDEV_ENGINE_MSVLD ] = &nve0_msvld_oclass; device->oclass[NVDEV_ENGINE_MSPDEC ] = &nve0_mspdec_oclass; device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass; @@ -119,9 +119,9 @@ nve0_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = nve4_gr_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nve0_disp_oclass; - device->oclass[NVDEV_ENGINE_CE0 ] = &nve0_ce0_oclass; - device->oclass[NVDEV_ENGINE_CE1 ] = &nve0_ce1_oclass; - device->oclass[NVDEV_ENGINE_CE2 ] = &nve0_ce2_oclass; + device->oclass[NVDEV_ENGINE_CE0 ] = &gk104_ce0_oclass; + device->oclass[NVDEV_ENGINE_CE1 ] = &gk104_ce1_oclass; + device->oclass[NVDEV_ENGINE_CE2 ] = &gk104_ce2_oclass; device->oclass[NVDEV_ENGINE_MSVLD ] = &nve0_msvld_oclass; device->oclass[NVDEV_ENGINE_MSPDEC ] = &nve0_mspdec_oclass; device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass; @@ -153,9 +153,9 @@ nve0_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = nve4_gr_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nve0_disp_oclass; - device->oclass[NVDEV_ENGINE_CE0 ] = &nve0_ce0_oclass; - device->oclass[NVDEV_ENGINE_CE1 ] = &nve0_ce1_oclass; - device->oclass[NVDEV_ENGINE_CE2 ] = &nve0_ce2_oclass; + device->oclass[NVDEV_ENGINE_CE0 ] = &gk104_ce0_oclass; + device->oclass[NVDEV_ENGINE_CE1 ] = &gk104_ce1_oclass; + device->oclass[NVDEV_ENGINE_CE2 ] = &gk104_ce2_oclass; device->oclass[NVDEV_ENGINE_MSVLD ] = &nve0_msvld_oclass; device->oclass[NVDEV_ENGINE_MSPDEC ] = &nve0_mspdec_oclass; device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass; @@ -178,7 +178,7 @@ nve0_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_FIFO ] = gk20a_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = gk20a_gr_oclass; - device->oclass[NVDEV_ENGINE_CE2 ] = &nve0_ce2_oclass; + device->oclass[NVDEV_ENGINE_CE2 ] = &gk104_ce2_oclass; device->oclass[NVDEV_ENGINE_PM ] = &nve0_pm_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &gk20a_volt_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = gk20a_pmu_oclass; @@ -209,9 +209,9 @@ nve0_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = nvf0_gr_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nvf0_disp_oclass; - device->oclass[NVDEV_ENGINE_CE0 ] = &nve0_ce0_oclass; - device->oclass[NVDEV_ENGINE_CE1 ] = &nve0_ce1_oclass; - device->oclass[NVDEV_ENGINE_CE2 ] = &nve0_ce2_oclass; + device->oclass[NVDEV_ENGINE_CE0 ] = &gk104_ce0_oclass; + device->oclass[NVDEV_ENGINE_CE1 ] = &gk104_ce1_oclass; + device->oclass[NVDEV_ENGINE_CE2 ] = &gk104_ce2_oclass; device->oclass[NVDEV_ENGINE_MSVLD ] = &nve0_msvld_oclass; device->oclass[NVDEV_ENGINE_MSPDEC ] = &nve0_mspdec_oclass; device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass; @@ -243,9 +243,9 @@ nve0_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = gk110b_gr_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nvf0_disp_oclass; - device->oclass[NVDEV_ENGINE_CE0 ] = &nve0_ce0_oclass; - device->oclass[NVDEV_ENGINE_CE1 ] = &nve0_ce1_oclass; - device->oclass[NVDEV_ENGINE_CE2 ] = &nve0_ce2_oclass; + device->oclass[NVDEV_ENGINE_CE0 ] = &gk104_ce0_oclass; + device->oclass[NVDEV_ENGINE_CE1 ] = &gk104_ce1_oclass; + device->oclass[NVDEV_ENGINE_CE2 ] = &gk104_ce2_oclass; device->oclass[NVDEV_ENGINE_MSVLD ] = &nve0_msvld_oclass; device->oclass[NVDEV_ENGINE_MSPDEC ] = &nve0_mspdec_oclass; device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass; @@ -277,9 +277,9 @@ nve0_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = nv108_gr_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nvf0_disp_oclass; - device->oclass[NVDEV_ENGINE_CE0 ] = &nve0_ce0_oclass; - device->oclass[NVDEV_ENGINE_CE1 ] = &nve0_ce1_oclass; - device->oclass[NVDEV_ENGINE_CE2 ] = &nve0_ce2_oclass; + device->oclass[NVDEV_ENGINE_CE0 ] = &gk104_ce0_oclass; + device->oclass[NVDEV_ENGINE_CE1 ] = &gk104_ce1_oclass; + device->oclass[NVDEV_ENGINE_CE2 ] = &gk104_ce2_oclass; device->oclass[NVDEV_ENGINE_MSVLD ] = &nve0_msvld_oclass; device->oclass[NVDEV_ENGINE_MSPDEC ] = &nve0_mspdec_oclass; device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass; @@ -310,9 +310,9 @@ nve0_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = nv108_gr_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nvf0_disp_oclass; - device->oclass[NVDEV_ENGINE_CE0 ] = &nve0_ce0_oclass; - device->oclass[NVDEV_ENGINE_CE1 ] = &nve0_ce1_oclass; - device->oclass[NVDEV_ENGINE_CE2 ] = &nve0_ce2_oclass; + device->oclass[NVDEV_ENGINE_CE0 ] = &gk104_ce0_oclass; + device->oclass[NVDEV_ENGINE_CE1 ] = &gk104_ce1_oclass; + device->oclass[NVDEV_ENGINE_CE2 ] = &gk104_ce2_oclass; device->oclass[NVDEV_ENGINE_MSVLD ] = &nve0_msvld_oclass; device->oclass[NVDEV_ENGINE_MSPDEC ] = &nve0_mspdec_oclass; device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass; -- 2.20.1