From bc7b34a2fb78661b2980d949aad8edc39c253e3a Mon Sep 17 00:00:00 2001 From: Peter De Schrijver Date: Tue, 25 Jul 2017 13:34:06 +0300 Subject: [PATCH] clk: tegra: Init cfg structure in _get_pll_mnp Not all fields are read from the hw depending on the PLL type. Make sure the other fields are 0 by clearing the structure beforehand to prevent users such as the rate re-calculation code from using bogus values. Based on work by Alex Frid Signed-off-by: Peter De Schrijver Tested-by: Thierry Reding Acked-by: Thierry Reding Signed-off-by: Stephen Boyd --- drivers/clk/tegra/clk-pll.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c index fbd8726213ab..1c36b8a72bd2 100644 --- a/drivers/clk/tegra/clk-pll.c +++ b/drivers/clk/tegra/clk-pll.c @@ -690,6 +690,8 @@ static void _get_pll_mnp(struct tegra_clk_pll *pll, struct tegra_clk_pll_params *params = pll->params; struct div_nmp *div_nmp = params->div_nmp; + *cfg = (struct tegra_clk_pll_freq_table) { }; + if ((params->flags & (TEGRA_PLLM | TEGRA_PLLMB)) && (pll_override_readl(PMC_PLLP_WB0_OVERRIDE, pll) & PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE)) { -- 2.20.1