From ba9c0bbbe8cf3b81906078eab16419592054da09 Mon Sep 17 00:00:00 2001 From: Sunyoung Kang Date: Mon, 28 May 2018 17:31:38 +0900 Subject: [PATCH] [9610] arm64: dts: add MFC device tree This adds the MFC device tree file: exynos9610-mfc.dtsi Change-Id: If7f27ec043bac4a852f6fa21573b343db421bf31 Signed-off-by: Sunyoung Kang --- .../arm64/boot/dts/exynos/exynos9610-mfc.dtsi | 198 ++++++++++++++++++ arch/arm64/boot/dts/exynos/exynos9610.dtsi | 4 +- 2 files changed, 201 insertions(+), 1 deletion(-) create mode 100644 arch/arm64/boot/dts/exynos/exynos9610-mfc.dtsi diff --git a/arch/arm64/boot/dts/exynos/exynos9610-mfc.dtsi b/arch/arm64/boot/dts/exynos/exynos9610-mfc.dtsi new file mode 100644 index 000000000000..ad779cc39c26 --- /dev/null +++ b/arch/arm64/boot/dts/exynos/exynos9610-mfc.dtsi @@ -0,0 +1,198 @@ +/* + * SAMSUNG EXYNOS SoC mfc device tree source + * + * Copyright (c) 2018 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * SAMSUNG EXYNOS SoC mfc device nodes are listed in this file. + * EXYNOS based board files can include this file and provide + * values for board specfic bindings. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include "exynos9610-sysmmu.dtsi" + +/ { + mfc_0: mfc0@12C30000 { + /* Basic setting */ + compatible = "samsung,exynos-mfc"; + reg = <0x0 0x12C30000 0x10000>; + interrupts = <0 175 0>; + clock-names = "aclk_mfc"; + clocks = <&clock GATE_MFC_QCH>; + iommus = <&sysmmu_mfc0>, <&sysmmu_mfc1>; + + /* MFC version */ + ip_ver = <0x1202>; + + /* Debug mode */ + debug_mode = <1>; + + /* Sysmmu check */ + share_sysmmu = <0>; + axid_mask = <0xFFFF>; + mfc_fault_num = <0x0>; + + /* Features */ + nal_q = <1 0x0>; + skype = <1 0x0>; + black_bar = <1 0x0>; + color_aspect_dec = <1 0x0>; + static_info_dec = <1 0x0>; + color_aspect_enc = <1 0x0>; + static_info_enc = <1 0x180314>; + + /* Encoder default parameter: max number is 100 */ + enc_param_num = <25>; + enc_param_addr = <0xF7B4 0xF7B8 0xF7B0 0xF798 0xFA2C + 0xF790 0xFA34 0xFA38 0xFA3C 0xF7C0 + 0xF7C8 0xF7CC 0xFA60 0xFDD4 0xFDDC + 0xFB54 0xFB58 0xFBA8 0xFD90 0xFD94 + 0xFD40 0xFD48 0xFD4C 0xFD50 0xFD80>; + enc_param_val = <0x100 0x100 0x0 0x4000 0x3FD00 + 0x0 0x0 0x2710 0x3E8 0x0 + 0x0 0x0 0x0 0x8050D215 0x0 + 0x3011 0x0 0x0 0x2D 0xA00 + 0x1D 0xF4240 0x33003300 0x2 0x1>; + + /* QoS */ + num_qos_steps = <8>; + max_qos_steps = <9>; + max_mb = <4624565>; + mfc_freq_control = <0>; + mo_control = <0>; + bw_control = <1>; + + /* Sub nodes for sysmmu, hwfc and mmcache */ + #address-cells = <2>; + #size-cells = <1>; + ranges; + iommu { + reg = <0x0 0x12C70000 0x9000>, + <0x0 0x12C90000 0x9000>; + }; + hwfc { + reg = <0x0 0x17628000 0x100>; + }; + + /* QoS table */ + mfc_qos_table { + mfc_qos_variant_0 { + thrd_mb = <0>; + freq_mfc = <100000>; + freq_int = <100000>; + freq_mif = <419000>; + freq_cpu = <0>; + freq_kfc = <0>; + mo_value = <0>; + mo_10bit_value = <0>; + mo_uhd_enc60_value = <0>; + time_fw = <830>; + }; + mfc_qos_variant_1 { + thrd_mb = <254973>; + freq_mfc = <200000>; + freq_int = <200000>; + freq_mif = <546000>; + freq_cpu = <0>; + freq_kfc = <0>; + mo_value = <0>; + mo_10bit_value = <0>; + mo_uhd_enc60_value = <0>; + time_fw = <477>; + }; + mfc_qos_variant_2 { + thrd_mb = <520087>; + freq_mfc = <400000>; + freq_int = <400000>; + freq_mif = <845000>; + freq_cpu = <0>; + freq_kfc = <0>; + mo_value = <0>; + mo_10bit_value = <0>; + mo_uhd_enc60_value = <0>; + time_fw = <282>; + }; + mfc_qos_variant_3 { + thrd_mb = <1080460>; + freq_mfc = <533000>; + freq_int = <533000>; + freq_mif = <1014000>; + freq_cpu = <0>; + freq_kfc = <0>; + mo_value = <0>; + mo_10bit_value = <0>; + mo_uhd_enc60_value = <0>; + time_fw = <218>; + }; + mfc_qos_variant_4 { + thrd_mb = <1686802>; + freq_mfc = <533000>; + freq_int = <533000>; + freq_mif = <1539000>; + freq_cpu = <0>; + freq_kfc = <0>; + mo_value = <0>; + mo_10bit_value = <0>; + mo_uhd_enc60_value = <0>; + time_fw = <184>; + }; + mfc_qos_variant_5 { + thrd_mb = <2343032>; + freq_mfc = <666000>; + freq_int = <667000>; + freq_mif = <1794000>; + freq_cpu = <0>; + freq_kfc = <0>; + mo_value = <1>; + mo_10bit_value = <0>; + mo_uhd_enc60_value = <0>; + time_fw = <157>; + }; + mfc_qos_variant_6 { + thrd_mb = <3099259>; + freq_mfc = <666000>; + freq_int = <667000>; + freq_mif = <2093000>; + freq_cpu = <0>; + freq_kfc = <0>; + mo_value = <1>; + mo_10bit_value = <0>; + mo_uhd_enc60_value = <0>; + time_fw = <151>; + }; + mfc_qos_variant_7 { + thrd_mb = <4216920>; + freq_mfc = <666000>; + freq_int = <667000>; + freq_mif = <2093000>; + freq_cpu = <0>; + freq_kfc = <0>; + mo_value = <0>; + mo_10bit_value = <1>; + mo_uhd_enc60_value = <0>; + time_fw = <151>; + }; + /* special level for uhd 60fps enc */ + mfc_qos_variant_8 { + thrd_mb = <1686802>; + freq_mfc = <533000>; + freq_int = <533000>; + freq_mif = <1539000>; + freq_cpu = <0>; + freq_kfc = <0>; + mo_value = <0>; + mo_10bit_value = <0>; + mo_uhd_enc60_value = <1>; + time_fw = <184>; + }; + + }; + }; +}; + diff --git a/arch/arm64/boot/dts/exynos/exynos9610.dtsi b/arch/arm64/boot/dts/exynos/exynos9610.dtsi index 7756a0c8853d..dfbb90d8ecd9 100644 --- a/arch/arm64/boot/dts/exynos/exynos9610.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos9610.dtsi @@ -23,6 +23,7 @@ #include #include "exynos9610-pm-domains.dtsi" #include +#include "exynos9610-mfc.dtsi" / { compatible = "samsung,armv8", "samsung,exynos9610"; @@ -103,6 +104,7 @@ dsim0 = &dsim_0; decon0 = &decon_f; scaler0 = &scaler_0; + mfc0 = &mfc_0; }; chipid@10000000 { @@ -2702,7 +2704,7 @@ #size-cells = <1>; ranges; - domain-clients = <>; + domain-clients = <&mfc_0>; }; iommu-domain_g2dmscljpeg { -- 2.20.1