From ab8cb86644e162eaa68d0dc7a423dfdf857fce85 Mon Sep 17 00:00:00 2001 From: Ayoung Sim Date: Tue, 4 Sep 2018 15:40:27 +0900 Subject: [PATCH] [RAMEN9610-10029][COMMON] media: mfc: support decoded order decoding If the DECODING_ORDER_ENABLE is set, F/W returns decoded information in same register. frame type, status and addr are same whether decoded or display. Change-Id: I92b1c8a21205258bce2a13262d59b6663476ff93 Signed-off-by: Ayoung Sim --- drivers/media/platform/exynos/mfc/exynos_mfc_media.h | 2 ++ drivers/media/platform/exynos/mfc/mfc_cmd.c | 4 ++++ drivers/media/platform/exynos/mfc/mfc_data_struct.h | 1 + drivers/media/platform/exynos/mfc/mfc_dec_internal.h | 10 ++++++++++ drivers/media/platform/exynos/mfc/mfc_dec_v4l2.c | 3 +++ drivers/media/platform/exynos/mfc/mfc_regs.h | 7 ++++--- 6 files changed, 24 insertions(+), 3 deletions(-) diff --git a/drivers/media/platform/exynos/mfc/exynos_mfc_media.h b/drivers/media/platform/exynos/mfc/exynos_mfc_media.h index f75062c8a09c..5e93f31c13e1 100644 --- a/drivers/media/platform/exynos/mfc/exynos_mfc_media.h +++ b/drivers/media/platform/exynos/mfc/exynos_mfc_media.h @@ -431,6 +431,8 @@ enum v4l2_mpeg_video_hevc_hierarchical_coding_type { (V4L2_CID_MPEG_MFC_BASE + 198) #define V4L2_CID_MPEG_VIDEO_HIERARCHICAL_BITRATE_CTRL \ (V4L2_CID_MPEG_MFC_BASE + 199) +#define V4L2_CID_MPEG_VIDEO_DECODING_ORDER \ + (V4L2_CID_MPEG_MFC_BASE + 200) /* QP BOUND interface */ #define V4L2_CID_MPEG_VIDEO_H264_MAX_QP_P \ diff --git a/drivers/media/platform/exynos/mfc/mfc_cmd.c b/drivers/media/platform/exynos/mfc/mfc_cmd.c index 9323384d08fc..7e54f3de37a1 100644 --- a/drivers/media/platform/exynos/mfc/mfc_cmd.c +++ b/drivers/media/platform/exynos/mfc/mfc_cmd.c @@ -207,6 +207,10 @@ void mfc_cmd_dec_seq_header(struct mfc_ctx *ctx) /* Parsing all including PPS */ reg |= (0x1 << MFC_REG_D_DEC_OPT_SPECIAL_PARSING_SHIFT); + /* Enabe decoding order */ + if (dec->decoding_order) + reg |= (0x1 << MFC_REG_D_DEC_OPT_DECODING_ORDER_ENABLE); + MFC_WRITEL(reg, MFC_REG_D_DEC_OPTIONS); MFC_WRITEL(MFC_CONCEAL_COLOR, MFC_REG_D_FORCE_PIXEL_VAL); diff --git a/drivers/media/platform/exynos/mfc/mfc_data_struct.h b/drivers/media/platform/exynos/mfc/mfc_data_struct.h index 5140316c92dc..5ff8764f7d2e 100644 --- a/drivers/media/platform/exynos/mfc/mfc_data_struct.h +++ b/drivers/media/platform/exynos/mfc/mfc_data_struct.h @@ -1358,6 +1358,7 @@ struct mfc_dec { unsigned int color_range; unsigned int color_space; + unsigned int decoding_order; /* * new variables should be added above * ============ boundary line ============ diff --git a/drivers/media/platform/exynos/mfc/mfc_dec_internal.h b/drivers/media/platform/exynos/mfc/mfc_dec_internal.h index cdf8cc6952eb..664ba2888ed3 100644 --- a/drivers/media/platform/exynos/mfc/mfc_dec_internal.h +++ b/drivers/media/platform/exynos/mfc/mfc_dec_internal.h @@ -544,6 +544,16 @@ static struct v4l2_queryctrl controls[] = { .step = 1, .default_value = 0, }, + { + .id = V4L2_CID_MPEG_VIDEO_DECODING_ORDER, + .type = V4L2_CTRL_TYPE_BOOLEAN, + .name = "decoding order enable", + .minimum = 0, + .maximum = 1, + .step = 1, + .default_value = 0, + }, + }; #define NUM_CTRLS ARRAY_SIZE(controls) diff --git a/drivers/media/platform/exynos/mfc/mfc_dec_v4l2.c b/drivers/media/platform/exynos/mfc/mfc_dec_v4l2.c index fe2730862371..efebbfa0b373 100644 --- a/drivers/media/platform/exynos/mfc/mfc_dec_v4l2.c +++ b/drivers/media/platform/exynos/mfc/mfc_dec_v4l2.c @@ -1117,6 +1117,9 @@ static int mfc_dec_s_ctrl(struct file *file, void *priv, mfc_debug(2, "[MEMINFO][HDR+] shared handle fd: %d, vaddr: 0x%p\n", dec->sh_handle_hdr.fd, dec->sh_handle_hdr.vaddr); break; + case V4L2_CID_MPEG_VIDEO_DECODING_ORDER: + dec->decoding_order = ctrl->value; + break; default: list_for_each_entry(ctx_ctrl, &ctx->ctrls, list) { if (!(ctx_ctrl->type & MFC_CTRL_TYPE_SET)) diff --git a/drivers/media/platform/exynos/mfc/mfc_regs.h b/drivers/media/platform/exynos/mfc/mfc_regs.h index 792316370290..17e89acba767 100644 --- a/drivers/media/platform/exynos/mfc/mfc_regs.h +++ b/drivers/media/platform/exynos/mfc/mfc_regs.h @@ -618,11 +618,12 @@ #define MFC_REG_D_DEC_OPT_IDR_DECODING_MASK 0x1 #define MFC_REG_D_DEC_OPT_IDR_DECODING_SHIFT 6 #define MFC_REG_D_DEC_OPT_DISCARD_RCV_HEADER_SHIFT 7 -#define MFC_REG_D_DEC_OPT_CONCEAL_CONTROL_SHIFT 8 +#define MFC_REG_D_DEC_OPT_CONCEAL_CONTROL_SHIFT 8 #define MFC_REG_D_DEC_OPT_PARALLEL_DISABLE_SHIFT 11 -#define MFC_REG_D_DEC_OPT_REALLOC_CONTROL_SHIFT 13 -#define MFC_REG_D_DEC_OPT_SPECIAL_PARSING_SHIFT 15 +#define MFC_REG_D_DEC_OPT_REALLOC_CONTROL_SHIFT 13 +#define MFC_REG_D_DEC_OPT_SPECIAL_PARSING_SHIFT 15 #define MFC_REG_D_DEC_OPT_THUMBNAIL_DECODING 16 +#define MFC_REG_D_DEC_OPT_DECODING_ORDER_ENABLE 17 /* 0xF0C4: MFC_REG_D_SEI_ENABLE */ -- 2.20.1