From aa0330fbe60f18677fce0a113dcd979fa596da51 Mon Sep 17 00:00:00 2001 From: Kyungwoo Kang Date: Thu, 15 Jun 2017 14:58:22 +0900 Subject: [PATCH] [COMMON] i2c: exynos5: Add input clock setting scheme Since USI version 2 each I2C channel sets its input clock. Change-Id: I933038bd0373e2c18d915e67f85aad8a7904e761 Signed-off-by: Kyungwoo Kang --- drivers/i2c/busses/i2c-exynos5.c | 14 +++++++++++++- drivers/i2c/busses/i2c-exynos5.h | 3 +++ 2 files changed, 16 insertions(+), 1 deletion(-) diff --git a/drivers/i2c/busses/i2c-exynos5.c b/drivers/i2c/busses/i2c-exynos5.c index 6c4d0ac05849..04fa9d0e5d76 100644 --- a/drivers/i2c/busses/i2c-exynos5.c +++ b/drivers/i2c/busses/i2c-exynos5.c @@ -363,7 +363,7 @@ static void exynos5_i2c_clr_pend_irq(struct exynos5_i2c *i2c) */ static int exynos5_i2c_set_timing(struct exynos5_i2c *i2c, bool hs_timings) { - unsigned int ipclk = clk_get_rate(i2c->rate_clk); + unsigned int ipclk, ret; unsigned int op_clk = (mode == HSI2C_HIGH_SPD) ? i2c->hs_clock : i2c->fs_clock; @@ -371,6 +371,15 @@ static int exynos5_i2c_set_timing(struct exynos5_i2c *i2c, bool hs_timings) u32 fs_div, uTSCL_H_FS, uTSTART_HD_FS; u32 utemp; + if (i2c->default_clk) { + ret = clk_set_rate(i2c->rate_clk, i2c->default_clk); + + if (ret < 0) + dev_err(i2c->dev, "Failed to set clock\n"); + } + + ipclk = clk_get_rate(i2c->rate_clk); + if (mode == HSI2C_HIGH_SPD) { /* ipclk's unit is Hz, op_clk's unit is Hz */ hs_div = ipclk / (op_clk * 15); @@ -942,6 +951,9 @@ static int exynos5_i2c_probe(struct platform_device *pdev) return -ENOMEM; } + if (of_property_read_u32(np, "default-clk", &i2c->default_clk)) + dev_err(i2c->dev, "Failed to get default clk info\n"); + /* Mode of operation High/Fast Speed mode */ if (of_get_property(np, "samsung,hs-mode", NULL)) { i2c->speed_mode = HSI2C_HIGH_SPD; diff --git a/drivers/i2c/busses/i2c-exynos5.h b/drivers/i2c/busses/i2c-exynos5.h index be94eef105a0..2e7f59c34339 100644 --- a/drivers/i2c/busses/i2c-exynos5.h +++ b/drivers/i2c/busses/i2c-exynos5.h @@ -41,6 +41,9 @@ struct exynos5_i2c { unsigned int fs_clock; unsigned int hs_clock; + /* to set the source clock */ + unsigned int default_clk; + /* * HSI2C Controller can operate in * 1. High speed upto 3.4Mbps -- 2.20.1