From a00ecf2212be0196c7485786c7b0c0263dfbf88a Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Thu, 21 Apr 2016 10:23:10 +1000 Subject: [PATCH] drm/nouveau/gr/gk104-: share implementation of ppc exception init This was really inconsistent, some implementations could touch PPCs that didn't exist, others neglected to touch ones that did. Signed-off-by: Ben Skeggs --- .../gpu/drm/nouveau/nvkm/engine/gr/gf100.h | 2 ++ .../gpu/drm/nouveau/nvkm/engine/gr/gk104.c | 19 ++++++++++++++++++- .../gpu/drm/nouveau/nvkm/engine/gr/gk110.c | 1 + .../gpu/drm/nouveau/nvkm/engine/gr/gk110b.c | 1 + .../gpu/drm/nouveau/nvkm/engine/gr/gk208.c | 1 + .../gpu/drm/nouveau/nvkm/engine/gr/gm107.c | 7 ++++--- .../gpu/drm/nouveau/nvkm/engine/gr/gm200.c | 7 ++++--- 7 files changed, 31 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.h index 611888c0dbac..2b98abdb9270 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.h @@ -120,6 +120,7 @@ struct gf100_gr_func { int (*init)(struct gf100_gr *); void (*init_gpc_mmu)(struct gf100_gr *); void (*init_rop_active_fbps)(struct gf100_gr *); + void (*init_ppc_exceptions)(struct gf100_gr *); void (*set_hww_esr_report_mask)(struct gf100_gr *); const struct gf100_gr_pack *mmio; struct { @@ -139,6 +140,7 @@ int gf100_gr_rops(struct gf100_gr *); int gk104_gr_init(struct gf100_gr *); void gk104_gr_init_rop_active_fbps(struct gf100_gr *); +void gk104_gr_init_ppc_exceptions(struct gf100_gr *); int gk20a_gr_init(struct gf100_gr *); diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk104.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk104.c index c6a3f6d8a8ca..ec22da6c99fc 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk104.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk104.c @@ -188,6 +188,21 @@ gk104_gr_init_rop_active_fbps(struct gf100_gr *gr) nvkm_mask(device, 0x408958, 0x0000000f, fbp_count); /* crop */ } +void +gk104_gr_init_ppc_exceptions(struct gf100_gr *gr) +{ + struct nvkm_device *device = gr->base.engine.subdev.device; + int gpc, ppc; + + for (gpc = 0; gpc < gr->gpc_nr; gpc++) { + for (ppc = 0; ppc < gr->ppc_nr[gpc]; ppc++) { + if (!(gr->ppc_mask[gpc] & (1 << ppc))) + continue; + nvkm_wr32(device, PPC_UNIT(gpc, ppc, 0x038), 0xc0000000); + } + } +} + int gk104_gr_init(struct gf100_gr *gr) { @@ -260,8 +275,9 @@ gk104_gr_init(struct gf100_gr *gr) nvkm_mask(device, 0x419cc0, 0x00000008, 0x00000008); nvkm_mask(device, 0x419eb4, 0x00001000, 0x00001000); + gr->func->init_ppc_exceptions(gr); + for (gpc = 0; gpc < gr->gpc_nr; gpc++) { - nvkm_wr32(device, GPC_UNIT(gpc, 0x3038), 0xc0000000); nvkm_wr32(device, GPC_UNIT(gpc, 0x0420), 0xc0000000); nvkm_wr32(device, GPC_UNIT(gpc, 0x0900), 0xc0000000); nvkm_wr32(device, GPC_UNIT(gpc, 0x1028), 0xc0000000); @@ -324,6 +340,7 @@ static const struct gf100_gr_func gk104_gr = { .init = gk104_gr_init, .init_rop_active_fbps = gk104_gr_init_rop_active_fbps, + .init_ppc_exceptions = gk104_gr_init_ppc_exceptions, .mmio = gk104_gr_pack_mmio, .fecs.ucode = &gk104_gr_fecs_ucode, .gpccs.ucode = &gk104_gr_gpccs_ucode, diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk110.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk110.c index f18af8974103..f31b171a4102 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk110.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk110.c @@ -184,6 +184,7 @@ static const struct gf100_gr_func gk110_gr = { .init = gk104_gr_init, .init_rop_active_fbps = gk104_gr_init_rop_active_fbps, + .init_ppc_exceptions = gk104_gr_init_ppc_exceptions, .mmio = gk110_gr_pack_mmio, .fecs.ucode = &gk110_gr_fecs_ucode, .gpccs.ucode = &gk110_gr_gpccs_ucode, diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk110b.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk110b.c index 2f029cad40cd..d76dd178007f 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk110b.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk110b.c @@ -104,6 +104,7 @@ static const struct gf100_gr_func gk110b_gr = { .init = gk104_gr_init, .init_rop_active_fbps = gk104_gr_init_rop_active_fbps, + .init_ppc_exceptions = gk104_gr_init_ppc_exceptions, .mmio = gk110b_gr_pack_mmio, .fecs.ucode = &gk110_gr_fecs_ucode, .gpccs.ucode = &gk110_gr_gpccs_ucode, diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk208.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk208.c index 01eb0e8cd4d5..14bbe6ed02a9 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk208.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk208.c @@ -163,6 +163,7 @@ static const struct gf100_gr_func gk208_gr = { .init = gk104_gr_init, .init_rop_active_fbps = gk104_gr_init_rop_active_fbps, + .init_ppc_exceptions = gk104_gr_init_ppc_exceptions, .mmio = gk208_gr_pack_mmio, .fecs.ucode = &gk208_gr_fecs_ucode, .gpccs.ucode = &gk208_gr_gpccs_ucode, diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gm107.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gm107.c index 56b9669f076a..45f965f608a7 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gm107.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gm107.c @@ -316,7 +316,7 @@ gm107_gr_init(struct gf100_gr *gr) const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, gr->tpc_total); u32 data[TPC_MAX / 8] = {}; u8 tpcnr[GPC_MAX]; - int gpc, tpc, ppc, rop; + int gpc, tpc, rop; int i; nvkm_wr32(device, GPC_BCAST(0x0880), 0x00000000); @@ -377,9 +377,9 @@ gm107_gr_init(struct gf100_gr *gr) nvkm_wr32(device, 0x405844, 0x00ffffff); nvkm_mask(device, 0x419cc0, 0x00000008, 0x00000008); + gr->func->init_ppc_exceptions(gr); + for (gpc = 0; gpc < gr->gpc_nr; gpc++) { - for (ppc = 0; ppc < 2 /* gr->ppc_nr[gpc] */; ppc++) - nvkm_wr32(device, PPC_UNIT(gpc, ppc, 0x038), 0xc0000000); nvkm_wr32(device, GPC_UNIT(gpc, 0x0420), 0xc0000000); nvkm_wr32(device, GPC_UNIT(gpc, 0x0900), 0xc0000000); nvkm_wr32(device, GPC_UNIT(gpc, 0x1028), 0xc0000000); @@ -443,6 +443,7 @@ static const struct gf100_gr_func gm107_gr = { .init = gm107_gr_init, .init_rop_active_fbps = gk104_gr_init_rop_active_fbps, + .init_ppc_exceptions = gk104_gr_init_ppc_exceptions, .mmio = gm107_gr_pack_mmio, .fecs.ucode = &gm107_gr_fecs_ucode, .gpccs.ucode = &gm107_gr_gpccs_ucode, diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gm200.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gm200.c index d9f320fa7dce..4dfa4513bb6c 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gm200.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gm200.c @@ -68,7 +68,7 @@ gm200_gr_init(struct gf100_gr *gr) const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, gr->tpc_total); u32 data[TPC_MAX / 8] = {}; u8 tpcnr[GPC_MAX]; - int gpc, tpc, ppc, rop; + int gpc, tpc, rop; int i; gr->func->init_gpc_mmu(gr); @@ -126,9 +126,9 @@ gm200_gr_init(struct gf100_gr *gr) nvkm_wr32(device, 0x405844, 0x00ffffff); nvkm_mask(device, 0x419cc0, 0x00000008, 0x00000008); + gr->func->init_ppc_exceptions(gr); + for (gpc = 0; gpc < gr->gpc_nr; gpc++) { - for (ppc = 0; ppc < gr->ppc_nr[gpc]; ppc++) - nvkm_wr32(device, PPC_UNIT(gpc, ppc, 0x038), 0xc0000000); nvkm_wr32(device, GPC_UNIT(gpc, 0x0420), 0xc0000000); nvkm_wr32(device, GPC_UNIT(gpc, 0x0900), 0xc0000000); nvkm_wr32(device, GPC_UNIT(gpc, 0x1028), 0xc0000000); @@ -211,6 +211,7 @@ gm200_gr = { .init = gm200_gr_init, .init_gpc_mmu = gm200_gr_init_gpc_mmu, .init_rop_active_fbps = gm200_gr_init_rop_active_fbps, + .init_ppc_exceptions = gk104_gr_init_ppc_exceptions, .rops = gm200_gr_rops, .ppc_nr = 2, .grctx = &gm200_grctx, -- 2.20.1