From 9adb15b80bf1dc6b30a584e76efc876dfd029a13 Mon Sep 17 00:00:00 2001 From: Thomas Abraham Date: Tue, 8 Sep 2009 14:26:00 +0900 Subject: [PATCH] ARM: S3C6410: use correct divider_shift in setrate_clksrc() In s3c64xx_setrate_clksrc() we used sclk->shift, but actually need to use sclk->divider_shift to correctly calculate the value for the divider register. Signed-off-by: Thomas Abraham [ben-linux@fluff.org: Minor re-indentation of description] Signed-off-by: Ben Dooks --- arch/arm/plat-s3c64xx/s3c6400-clock.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/plat-s3c64xx/s3c6400-clock.c b/arch/arm/plat-s3c64xx/s3c6400-clock.c index febac1950d8..c972d2f8c27 100644 --- a/arch/arm/plat-s3c64xx/s3c6400-clock.c +++ b/arch/arm/plat-s3c64xx/s3c6400-clock.c @@ -302,8 +302,8 @@ static int s3c64xx_setrate_clksrc(struct clk *clk, unsigned long rate) return -EINVAL; val = __raw_readl(reg); - val &= ~(0xf << sclk->shift); - val |= (div - 1) << sclk->shift; + val &= ~(0xf << sclk->divider_shift); + val |= (div - 1) << sclk->divider_shift; __raw_writel(val, reg); return 0; -- 2.20.1