From 9a20b09285bbd75ccc2ca78233241f8e31d54a28 Mon Sep 17 00:00:00 2001 From: "Maciej W. Rozycki" Date: Wed, 27 May 2015 14:15:20 +0100 Subject: [PATCH] MIPS: tlb-r3k: Optimise a TLBWI barrier in TLB invalidation Replace an explicit barrier with a useful processor instruction in TLB invalidation, following several other such cases elsewhere in `tlb-r3k.c'. Signed-off-by: Maciej W. Rozycki Cc: James Hogan Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/10196/ Signed-off-by: Ralf Baechle --- arch/mips/mm/tlb-r3k.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/mips/mm/tlb-r3k.c b/arch/mips/mm/tlb-r3k.c index 49b7132069d0..2b75b8f880ed 100644 --- a/arch/mips/mm/tlb-r3k.c +++ b/arch/mips/mm/tlb-r3k.c @@ -45,10 +45,10 @@ static void local_flush_tlb_from(int entry) old_ctx = read_c0_entryhi() & ASID_MASK; write_c0_entrylo0(0); - for (; entry < current_cpu_data.tlbsize; entry++) { + while (entry < current_cpu_data.tlbsize) { write_c0_index(entry << 8); write_c0_entryhi((entry | 0x80000) << 12); - BARRIER; + entry++; /* BARRIER */ tlb_write_indexed(); } write_c0_entryhi(old_ctx); -- 2.20.1