From 9962fd017becf944d671da498ccaaea570452206 Mon Sep 17 00:00:00 2001 From: Brian Pomerantz Date: Mon, 12 Feb 2007 00:53:05 -0800 Subject: [PATCH] [PATCH] EDAC: e752x byte access fix The reading of the DRA registers should be a byte at a time (one register at a time) instead of 4 bytes at a time (four registers). Reading a dword at a time retrieves erroneous information from all but the first register. A change was made to read in each register in a loop prior to using the data in those registers. Signed-off-by: Brian Pomerantz Signed-off-by: Dave Jiang Signed-off-by: Doug Thompson Cc: Alan Cox Cc: Andi Kleen Cc: "Eric W. Biederman" Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- drivers/edac/e752x_edac.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/edac/e752x_edac.c b/drivers/edac/e752x_edac.c index ab9873924f4f..9abfc0dc3bae 100644 --- a/drivers/edac/e752x_edac.c +++ b/drivers/edac/e752x_edac.c @@ -782,7 +782,12 @@ static void e752x_init_csrows(struct mem_ctl_info *mci, struct pci_dev *pdev, u8 value; u32 dra, drc, cumul_size; - pci_read_config_dword(pdev, E752X_DRA, &dra); + dra = 0; + for (index=0; index < 4; index++) { + u8 dra_reg; + pci_read_config_byte(pdev, E752X_DRA+index, &dra_reg); + dra |= dra_reg << (index * 8); + } pci_read_config_dword(pdev, E752X_DRC, &drc); drc_chan = dual_channel_active(ddrcsr); drc_drbg = drc_chan + 1; /* 128 in dual mode, 64 in single */ -- 2.20.1