From 972072aa7992634ec642bf41679a53b7aa060dd1 Mon Sep 17 00:00:00 2001 From: Vladimir Kondratiev Date: Mon, 17 Mar 2014 15:34:15 +0200 Subject: [PATCH] wil6210: reset on power good Configure hardware to perform full reset on "power good". This mean, reset HW on system boot. This improves card stability. By default this is off. Signed-off-by: Vladimir Kondratiev Signed-off-by: John W. Linville --- drivers/net/wireless/ath/wil6210/main.c | 8 ++++++-- drivers/net/wireless/ath/wil6210/wil6210.h | 2 ++ 2 files changed, 8 insertions(+), 2 deletions(-) diff --git a/drivers/net/wireless/ath/wil6210/main.c b/drivers/net/wireless/ath/wil6210/main.c index bd27bee8241f..684762203a62 100644 --- a/drivers/net/wireless/ath/wil6210/main.c +++ b/drivers/net/wireless/ath/wil6210/main.c @@ -241,8 +241,9 @@ static void wil_target_reset(struct wil6210_priv *wil) /* register write */ #define W(a, v) iowrite32(v, wil->csr + HOSTADDR(a)) /* register set = read, OR, write */ -#define S(a, v) iowrite32(ioread32(wil->csr + HOSTADDR(a)) | v, \ - wil->csr + HOSTADDR(a)) +#define S(a, v) W(a, R(a) | v) + /* register clear = read, AND with inverted, write */ +#define C(a, v) W(a, R(a) & ~v) wil->hw_version = R(RGF_USER_FW_REV_ID); rev_id = wil->hw_version & 0xff; @@ -286,11 +287,14 @@ static void wil_target_reset(struct wil6210_priv *wil) if (rev_id == 2) W(RGF_PCIE_LOS_COUNTER_CTL, BIT(8)); + C(RGF_USER_CLKS_CTL_0, BIT_USER_CLKS_RST_PWGD); + wil_dbg_misc(wil, "Reset completed in %d ms\n", delay); #undef R #undef W #undef S +#undef C } void wil_mbox_ring_le2cpus(struct wil6210_mbox_ring *r) diff --git a/drivers/net/wireless/ath/wil6210/wil6210.h b/drivers/net/wireless/ath/wil6210/wil6210.h index b376399e68ca..f7d8f0ead23e 100644 --- a/drivers/net/wireless/ath/wil6210/wil6210.h +++ b/drivers/net/wireless/ath/wil6210/wil6210.h @@ -79,6 +79,8 @@ struct RGF_ICR { #define RGF_USER_MAC_CPU_0 (0x8801fc) #define RGF_USER_USER_SCRATCH_PAD (0x8802bc) #define RGF_USER_FW_REV_ID (0x880a8c) /* chip revision */ +#define RGF_USER_CLKS_CTL_0 (0x880abc) + #define BIT_USER_CLKS_RST_PWGD BIT(11) /* reset on "power good" */ #define RGF_USER_CLKS_CTL_SW_RST_VEC_0 (0x880b04) #define RGF_USER_CLKS_CTL_SW_RST_VEC_1 (0x880b08) #define RGF_USER_CLKS_CTL_SW_RST_VEC_2 (0x880b0c) -- 2.20.1