From 8fa1faf8373197343c1e292c6511302f34f04832 Mon Sep 17 00:00:00 2001 From: ChiHun Won Date: Sat, 26 May 2018 10:08:37 +0900 Subject: [PATCH] [9610] arm64: dts: updated dpu device tree Change-Id: I8366770fa3fd37473b377ea1968c7a106825bf66 Signed-off-by: ChiHun Won --- arch/arm64/boot/dts/exynos/exynos9610.dtsi | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/exynos/exynos9610.dtsi b/arch/arm64/boot/dts/exynos/exynos9610.dtsi index 92ce45c452dc..7756a0c8853d 100644 --- a/arch/arm64/boot/dts/exynos/exynos9610.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos9610.dtsi @@ -2403,7 +2403,9 @@ dpp_0: dpp@0x14884000 { /* GF */ compatible = "samsung,exynos9-dpp"; #pb-id-cells = <3>; + /* DPP, DPU_DMA, DPU_DMA_COMMON */ reg = <0x0 0x14884000 0x1000>, <0x0 0x14895000 0x1000>, <0x0 0x14880000 0x110>; + /* DPU_DMA IRQ, DPP IRQ */ interrupts = <0 210 0>, <0 214 0>; attr = <0x50087>; /* DPP/IDMA/HDR10/FLIP/BLOCK/AFBC */ }; @@ -2419,9 +2421,7 @@ dpp_2: dpp@0x14881000 { /* G0 */ compatible = "samsung,exynos9-dpp"; #pb-id-cells = <3>; - /* DPP, DPU_DMA, DPU_DMA_COMMON */ reg = <0x0 0x14881000 0x1000>, <0x0 0x14891000 0x1000>; - /* DPU_DMA IRQ, DPP IRQ */ interrupts = <0 208 0>, <0 212 0>; attr = <0x50006>; /* DPP/IDMA/FLIP/BLOCK */ }; @@ -2462,7 +2462,6 @@ /* clock */ clock-names = "aclk"; clocks = <&clock UMUX_CLKCMU_DISPAUD_BUS>; - }; decon_f: decon_f@0x148B0000 { @@ -2483,7 +2482,7 @@ max_win = <4>; default_win = <0>; - default_idma = <2>; + default_idma = <0>; psr_mode = <2>; /* 0: video mode, 1: DP command mode, 2: MIPI command mode */ trig_mode = <0>; /* 0: hw trigger, 1: sw trigger */ dsi_mode = <0>; /* 0: single dsi, 1: dual dsi */ @@ -2493,6 +2492,9 @@ /* 0: DSI0, 1: DSI1, 2: DSI2 */ out_idx = <0>; + /* power domain */ + pd_name = "pd-dispaud"; + #address-cells = <2>; #size-cells = <1>; ranges; -- 2.20.1