From 8e02676ffa6906a97de7f90772e9cdcb75ea6743 Mon Sep 17 00:00:00 2001 From: Torgue Alexandre Date: Wed, 31 Aug 2016 09:14:14 +0100 Subject: [PATCH] ARM: 8610/1: V7M: Add dsb before jumping in handler mode According to ARM AN321 (section 4.12): "If the vector table is in writable memory such as SRAM, either relocated by VTOR or a device dependent memory remapping mechanism, then architecturally a memory barrier instruction is required after the vector table entry is updated, and if the exception is to be activated immediately" Reviewed-by: Vladimir Murzin Signed-off-by: Maxime Coquelin Signed-off-by: Alexandre TORGUE Signed-off-by: Russell King --- arch/arm/mm/proc-v7m.S | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/mm/proc-v7m.S b/arch/arm/mm/proc-v7m.S index e6786f007a59..f6d333f09bfe 100644 --- a/arch/arm/mm/proc-v7m.S +++ b/arch/arm/mm/proc-v7m.S @@ -132,6 +132,7 @@ __v7m_setup_cont: badr r1, 1f ldr r5, [r12, #11 * 4] @ read the SVC vector entry str r1, [r12, #11 * 4] @ write the temporary SVC vector entry + dsb mov r6, lr @ save LR ldr sp, =init_thread_union + THREAD_START_SP cpsie i -- 2.20.1