From 8d9321fbe2be1b403ac861930ed87d4b36d9febc Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 3 Apr 2015 11:28:01 +0200 Subject: [PATCH] ARM: dts: Use last parent for clocks during power domain on/off Replace fixed parent with last parent (obtained with clk_get_parent()) of clocks for devices in mfc and disp power domains. This should improve behavior if such clocks were reparented by the drivers and new parents are different than those specified in DTS. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Javier Martinez Canillas Tested-by: Javier Martinez Canillas Signed-off-by: Kukjin Kim --- arch/arm/boot/dts/exynos5420.dtsi | 13 ++++--------- 1 file changed, 4 insertions(+), 9 deletions(-) diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi index 8ab442158e15..7bf7a618cbc6 100644 --- a/arch/arm/boot/dts/exynos5420.dtsi +++ b/arch/arm/boot/dts/exynos5420.dtsi @@ -264,9 +264,8 @@ mfc_pd: power-domain@10044060 { compatible = "samsung,exynos4210-pd"; reg = <0x10044060 0x20>; - clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MOUT_SW_ACLK333>, - <&clock CLK_MOUT_USER_ACLK333>; - clock-names = "oscclk", "pclk0", "clk0"; + clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MOUT_USER_ACLK333>; + clock-names = "oscclk", "clk0"; #power-domain-cells = <0>; }; @@ -280,16 +279,12 @@ compatible = "samsung,exynos4210-pd"; reg = <0x100440C0 0x20>; #power-domain-cells = <0>; - clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MOUT_SW_ACLK200>, + clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MOUT_USER_ACLK200_DISP1>, - <&clock CLK_MOUT_SW_ACLK300>, <&clock CLK_MOUT_USER_ACLK300_DISP1>, - <&clock CLK_MOUT_SW_ACLK400>, <&clock CLK_MOUT_USER_ACLK400_DISP1>, <&clock CLK_FIMD1>, <&clock CLK_MIXER>; - clock-names = "oscclk", "pclk0", "clk0", - "pclk1", "clk1", "pclk2", "clk2", - "asb0", "asb1"; + clock-names = "oscclk", "clk0", "clk1", "clk2", "asb0", "asb1"; }; pinctrl_0: pinctrl@13400000 { -- 2.20.1