From 8ca7e8c7595e21c68781f101bffbc5e800f3a26a Mon Sep 17 00:00:00 2001 From: Jaehyoung Choi Date: Wed, 2 May 2018 22:59:38 +0900 Subject: [PATCH] [9610] pinctrl: samsung: add initial definition of pinctrl for exynos9610 Change-Id: Ie628d29ab948bac4a31aa343087115fb174cc87f Signed-off-by: Jaehyoung Choi --- .../pinctrl/samsung/pinctrl-exynos-arm64.c | 144 ++++++++++++++++++ drivers/pinctrl/samsung/pinctrl-exynos.h | 29 ++++ drivers/pinctrl/samsung/pinctrl-samsung.c | 3 + drivers/pinctrl/samsung/pinctrl-samsung.h | 1 + 4 files changed, 177 insertions(+) diff --git a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c index 0ab88fc268ea..bbf05ca68e28 100644 --- a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c +++ b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c @@ -45,6 +45,24 @@ static const struct samsung_pin_bank_type exynos5433_bank_type_alive = { .reg_offset = { 0x00, 0x04, 0x08, 0x0c, }, }; + +/* bank type for non-alive type + * (CON bit field: 4, DAT bit field: 1, PUD bit field: 4, DRV bit field: 4) + * (CONPDN bit field: 2, PUDPDN bit field: 4) + */ +static struct samsung_pin_bank_type bank_type_6 = { + .fld_width = { 4, 1, 4, 4, 2, 4, }, + .reg_offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, }, +}; + +/* bank type for alive type + * (CON bit field: 4, DAT bit field: 1, PUD bit field: 4, DRV bit field: 4) + */ +static struct samsung_pin_bank_type bank_type_7 = { + .fld_width = { 4, 1, 4, 4, }, + .reg_offset = { 0x00, 0x04, 0x08, 0x0c, }, +}; + /* Pad retention control code for accessing PMU regmap */ static atomic_t exynos_shared_retention_refcnt; @@ -407,3 +425,129 @@ const struct samsung_pinctrl_of_match_data exynos7_of_data __initconst = { .ctrl = exynos7_pin_ctrl, .num_ctrl = ARRAY_SIZE(exynos7_pin_ctrl), }; + +/* pin banks of exynos9610 pin-controller 0 (ALIVE) */ +static struct samsung_pin_bank_data exynos9610_pin_banks0[] = { + EXYNOS8_PIN_BANK_EINTN(bank_type_7, 6, 0x000, "etc1"), + EXYNOS8_PIN_BANK_EINTW(bank_type_7, 8, 0x020, "gpa0", 0x00), + EXYNOS8_PIN_BANK_EINTW(bank_type_7, 8, 0x040, "gpa1", 0x04), + EXYNOS8_PIN_BANK_EINTW(bank_type_7, 8, 0x060, "gpa2", 0x08), + EXYNOS8_PIN_BANK_EINTW(bank_type_7, 8, 0x080, "gpq0", 0x0c), +}; + +/* pin banks of exynos9610 pin-controller 1 (CMGP) */ +static struct samsung_pin_bank_data exynos9610_pin_banks1[] = { + EXYNOS8_PIN_BANK_EINTG(bank_type_7, 1, 0x000, "gpm0", 0x00), + EXYNOS8_PIN_BANK_EINTG(bank_type_7, 1, 0x020, "gpm1", 0x04), + EXYNOS8_PIN_BANK_EINTG(bank_type_7, 1, 0x040, "gpm2", 0x08), + EXYNOS8_PIN_BANK_EINTG(bank_type_7, 1, 0x060, "gpm3", 0x0C), + EXYNOS8_PIN_BANK_EINTG(bank_type_7, 1, 0x080, "gpm4", 0x10), + EXYNOS8_PIN_BANK_EINTG(bank_type_7, 1, 0x0A0, "gpm5", 0x14), + EXYNOS8_PIN_BANK_EINTG(bank_type_7, 1, 0x0C0, "gpm6", 0x18), + EXYNOS8_PIN_BANK_EINTG(bank_type_7, 1, 0x0E0, "gpm7", 0x1C), + EXYNOS8_PIN_BANK_EINTG(bank_type_7, 1, 0x100, "gpm8", 0x20), + EXYNOS8_PIN_BANK_EINTG(bank_type_7, 1, 0x120, "gpm9", 0x24), + EXYNOS8_PIN_BANK_EINTG(bank_type_7, 1, 0x140, "gpm10", 0x28), + EXYNOS8_PIN_BANK_EINTG(bank_type_7, 1, 0x160, "gpm11", 0x2C), + EXYNOS8_PIN_BANK_EINTG(bank_type_7, 1, 0x180, "gpm12", 0x30), + EXYNOS8_PIN_BANK_EINTG(bank_type_7, 1, 0x1A0, "gpm13", 0x34), + EXYNOS8_PIN_BANK_EINTG(bank_type_7, 1, 0x1C0, "gpm14", 0x38), + EXYNOS8_PIN_BANK_EINTG(bank_type_7, 1, 0x1E0, "gpm15", 0x3C), + EXYNOS8_PIN_BANK_EINTG(bank_type_7, 1, 0x200, "gpm16", 0x40), + EXYNOS8_PIN_BANK_EINTG(bank_type_7, 1, 0x220, "gpm17", 0x44), + EXYNOS8_PIN_BANK_EINTG(bank_type_7, 1, 0x240, "gpm18", 0x48), + EXYNOS8_PIN_BANK_EINTG(bank_type_7, 1, 0x260, "gpm19", 0x4C), + EXYNOS8_PIN_BANK_EINTG(bank_type_7, 1, 0x280, "gpm20", 0x50), + EXYNOS8_PIN_BANK_EINTG(bank_type_7, 1, 0x2A0, "gpm21", 0x54), + EXYNOS8_PIN_BANK_EINTG(bank_type_7, 1, 0x2C0, "gpm22", 0x58), + EXYNOS8_PIN_BANK_EINTG(bank_type_7, 1, 0x2E0, "gpm23", 0x5C), + EXYNOS8_PIN_BANK_EINTG(bank_type_7, 1, 0x300, "gpm24", 0x60), + EXYNOS8_PIN_BANK_EINTG(bank_type_7, 1, 0x320, "gpm25", 0x64), +}; + +/* pin banks of exynos9610 pin-controller 2 (DISPAUD) */ +static struct samsung_pin_bank_data exynos9610_pin_banks2[] = { + EXYNOS8_PIN_BANK_EINTG(bank_type_6, 5, 0x000, "gpb0", 0x00), + EXYNOS8_PIN_BANK_EINTG(bank_type_6, 4, 0x020, "gpb1", 0x04), + EXYNOS8_PIN_BANK_EINTG(bank_type_6, 5, 0x040, "gpb2", 0x08), +}; + +/* pin banks of exynos9610 pin-controller 3 (FSYS) */ +static struct samsung_pin_bank_data exynos9610_pin_banks3[] = { + EXYNOS8_PIN_BANK_EINTG(bank_type_6, 4, 0x000, "gpf0", 0x00), + EXYNOS8_PIN_BANK_EINTG(bank_type_6, 8, 0x020, "gpf1", 0x04), + EXYNOS8_PIN_BANK_EINTG(bank_type_6, 6, 0x040, "gpf2", 0x08), +}; + +/* pin banks of exynos9610 pin-controller 4 (TOP) */ +static struct samsung_pin_bank_data exynos9610_pin_banks4[] = { + EXYNOS8_PIN_BANK_EINTG(bank_type_6, 8, 0x000, "gpp0", 0x00), + EXYNOS8_PIN_BANK_EINTG(bank_type_6, 6, 0x020, "gpp1", 0x04), + EXYNOS8_PIN_BANK_EINTG(bank_type_6, 8, 0x040, "gpp2", 0x08), + EXYNOS8_PIN_BANK_EINTG(bank_type_6, 8, 0x060, "gpc0", 0x0C), + EXYNOS8_PIN_BANK_EINTG(bank_type_6, 8, 0x080, "gpc1", 0x10), + EXYNOS8_PIN_BANK_EINTG(bank_type_6, 5, 0x0A0, "gpc2", 0x14), + EXYNOS8_PIN_BANK_EINTG(bank_type_6, 8, 0x0C0, "gpg0", 0x18), + EXYNOS8_PIN_BANK_EINTG(bank_type_6, 8, 0x0E0, "gpg1", 0x1C), + EXYNOS8_PIN_BANK_EINTG(bank_type_6, 8, 0x100, "gpg2", 0x20), + EXYNOS8_PIN_BANK_EINTG(bank_type_6, 6, 0x120, "gpg3", 0x24), + EXYNOS8_PIN_BANK_EINTG(bank_type_6, 3, 0x140, "gpg4", 0x28), +}; + +/* pin banks of exynos9610 pin-controller 5 (SHUB) */ +static struct samsung_pin_bank_data exynos9610_pin_banks5[] = { + EXYNOS8_PIN_BANK_EINTG(bank_type_6, 4, 0x000, "gph0", 0x00), + EXYNOS8_PIN_BANK_EINTG(bank_type_6, 3, 0x020, "gph1", 0x04), +}; + +const struct samsung_pin_ctrl exynos9610_pin_ctrl[] = { + { + /* pin-controller instance 0 ALIVE data */ + .pin_banks = exynos9610_pin_banks0, + .nr_banks = ARRAY_SIZE(exynos9610_pin_banks0), + .eint_gpio_init = exynos_eint_gpio_init, + .eint_wkup_init = exynos_eint_wkup_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + }, { + /* pin-controller instance 1 AUD data */ + .pin_banks = exynos9610_pin_banks1, + .nr_banks = ARRAY_SIZE(exynos9610_pin_banks1), + //.eint_gpio_init = exynos_eint_gpio_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + }, { + /* pin-controller instance 2 CHUB data */ + .pin_banks = exynos9610_pin_banks2, + .nr_banks = ARRAY_SIZE(exynos9610_pin_banks2), + .eint_gpio_init = exynos_eint_gpio_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + }, { + /* pin-controller instance 3 CMGP data */ + .pin_banks = exynos9610_pin_banks3, + .nr_banks = ARRAY_SIZE(exynos9610_pin_banks3), + .eint_gpio_init = exynos_eint_gpio_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + }, { + /* pin-controller instance 4 FSYS0 data */ + .pin_banks = exynos9610_pin_banks4, + .nr_banks = ARRAY_SIZE(exynos9610_pin_banks4), + .eint_gpio_init = exynos_eint_gpio_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + }, { + /* pin-controller instance 5 FSYS1 data */ + .pin_banks = exynos9610_pin_banks5, + .nr_banks = ARRAY_SIZE(exynos9610_pin_banks5), + .eint_gpio_init = exynos_eint_gpio_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + }, +}; + +const struct samsung_pinctrl_of_match_data exynos9610_of_data __initconst = { + .ctrl = exynos9610_pin_ctrl, + .num_ctrl = ARRAY_SIZE(exynos9610_pin_ctrl), +}; diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.h b/drivers/pinctrl/samsung/pinctrl-exynos.h index 7639b926c5c1..db3c3d328ef3 100644 --- a/drivers/pinctrl/samsung/pinctrl-exynos.h +++ b/drivers/pinctrl/samsung/pinctrl-exynos.h @@ -112,6 +112,35 @@ .pctl_res_idx = pctl_idx, \ } \ +#define EXYNOS8_PIN_BANK_EINTN(types, pins, reg, id) \ + { \ + .type = &types, \ + .pctl_offset = reg, \ + .nr_pins = pins, \ + .eint_type = EINT_TYPE_NONE, \ + .name = id \ + } + +#define EXYNOS8_PIN_BANK_EINTG(types, pins, reg, id, offs) \ + { \ + .type = &types, \ + .pctl_offset = reg, \ + .nr_pins = pins, \ + .eint_type = EINT_TYPE_GPIO, \ + .eint_offset = offs, \ + .name = id \ + } + +#define EXYNOS8_PIN_BANK_EINTW(types, pins, reg, id, offs) \ + { \ + .type = &types, \ + .pctl_offset = reg, \ + .nr_pins = pins, \ + .eint_type = EINT_TYPE_WKUP, \ + .eint_offset = offs, \ + .name = id \ + } + /** * struct exynos_weint_data: irq specific data for all the wakeup interrupts * generated by the external wakeup interrupt controller. diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.c b/drivers/pinctrl/samsung/pinctrl-samsung.c index c5420f3b45aa..70d7a2386911 100644 --- a/drivers/pinctrl/samsung/pinctrl-samsung.c +++ b/drivers/pinctrl/samsung/pinctrl-samsung.c @@ -1232,6 +1232,9 @@ static const struct of_device_id samsung_pinctrl_dt_match[] = { .data = &exynos5433_of_data }, { .compatible = "samsung,exynos7-pinctrl", .data = &exynos7_of_data }, + { .compatible = "samsung,exynos9610-pinctrl", + .data = &exynos9610_of_data }, + #endif #ifdef CONFIG_PINCTRL_S3C64XX { .compatible = "samsung,s3c64xx-pinctrl", diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.h b/drivers/pinctrl/samsung/pinctrl-samsung.h index 102c9de55ed2..2b9b6c659f8b 100644 --- a/drivers/pinctrl/samsung/pinctrl-samsung.h +++ b/drivers/pinctrl/samsung/pinctrl-samsung.h @@ -342,5 +342,6 @@ extern const struct samsung_pinctrl_of_match_data s3c2416_of_data; extern const struct samsung_pinctrl_of_match_data s3c2440_of_data; extern const struct samsung_pinctrl_of_match_data s3c2450_of_data; extern const struct samsung_pinctrl_of_match_data s5pv210_of_data; +extern const struct samsung_pinctrl_of_match_data exynos9610_of_data; #endif /* __PINCTRL_SAMSUNG_H */ -- 2.20.1