From 8a52fd9f240a6e2b73361fb825145f9951fc552d Mon Sep 17 00:00:00 2001 From: Paulo Zanoni Date: Wed, 31 Oct 2012 18:12:51 -0200 Subject: [PATCH] drm/i915: use CPU and PCH transcoders on lpt_disable_pch_transcoder ... instead of "pipe", which is wrong. Signed-off-by: Paulo Zanoni Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_display.c | 18 ++++++++---------- 1 file changed, 8 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 787e62a44542..1b57fbc5eb5b 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -1766,22 +1766,20 @@ static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv, } static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv, - enum pipe pipe) + enum transcoder cpu_transcoder) { - int reg; u32 val; /* FDI relies on the transcoder */ - assert_fdi_tx_disabled(dev_priv, pipe); - assert_fdi_rx_disabled(dev_priv, pipe); + assert_fdi_tx_disabled(dev_priv, cpu_transcoder); + assert_fdi_rx_disabled(dev_priv, TRANSCODER_A); - reg = TRANSCONF(pipe); - val = I915_READ(reg); + val = I915_READ(_TRANSACONF); val &= ~TRANS_ENABLE; - I915_WRITE(reg, val); + I915_WRITE(_TRANSACONF, val); /* wait for PCH transcoder off, transcoder state */ - if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50)) - DRM_ERROR("failed to disable transcoder %d\n", pipe); + if (wait_for((I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE) == 0, 50)) + DRM_ERROR("Failed to disable PCH transcoder\n"); } /** @@ -3630,7 +3628,7 @@ static void haswell_crtc_disable(struct drm_crtc *crtc) if (is_pch_port) { ironlake_fdi_disable(crtc); - lpt_disable_pch_transcoder(dev_priv, pipe); + lpt_disable_pch_transcoder(dev_priv, cpu_transcoder); intel_disable_pch_pll(intel_crtc); ironlake_fdi_pll_disable(intel_crtc); } -- 2.20.1