From 872deb21038e90903a40ab6a29b9d0652a6ebc8d Mon Sep 17 00:00:00 2001 From: Shyam Sundar S K Date: Fri, 2 Dec 2016 00:44:28 +0530 Subject: [PATCH] NTB: Register and offset values fix for memory window Due to incorrect limit and translation register values, NTB link was going down when the memory window was setup. Made appropriate changes as per spec. Fix limit register values for BAR1, which was overlapping with the BAR23 address. Signed-off-by: Shyam Sundar S K Acked-by: Allen Hubbe Signed-off-by: Jon Mason --- drivers/ntb/hw/amd/ntb_hw_amd.c | 14 ++++---------- 1 file changed, 4 insertions(+), 10 deletions(-) diff --git a/drivers/ntb/hw/amd/ntb_hw_amd.c b/drivers/ntb/hw/amd/ntb_hw_amd.c index b33f13b5b69d..774918ca63d2 100644 --- a/drivers/ntb/hw/amd/ntb_hw_amd.c +++ b/drivers/ntb/hw/amd/ntb_hw_amd.c @@ -138,11 +138,11 @@ static int amd_ntb_mw_set_trans(struct ntb_dev *ntb, int idx, base_addr = pci_resource_start(ndev->ntb.pdev, bar); if (bar != 1) { - xlat_reg = AMD_BAR23XLAT_OFFSET + ((bar - 2) << 3); - limit_reg = AMD_BAR23LMT_OFFSET + ((bar - 2) << 3); + xlat_reg = AMD_BAR23XLAT_OFFSET + ((bar - 2) << 2); + limit_reg = AMD_BAR23LMT_OFFSET + ((bar - 2) << 2); /* Set the limit if supported */ - limit = base_addr + size; + limit = size; /* set and verify setting the translation address */ write64(addr, peer_mmio + xlat_reg); @@ -164,14 +164,8 @@ static int amd_ntb_mw_set_trans(struct ntb_dev *ntb, int idx, xlat_reg = AMD_BAR1XLAT_OFFSET; limit_reg = AMD_BAR1LMT_OFFSET; - /* split bar addr range must all be 32 bit */ - if (addr & (~0ull << 32)) - return -EINVAL; - if ((addr + size) & (~0ull << 32)) - return -EINVAL; - /* Set the limit if supported */ - limit = base_addr + size; + limit = size; /* set and verify setting the translation address */ write64(addr, peer_mmio + xlat_reg); -- 2.20.1