From 835ed7bf12609ce23d42956e74206cc539a0ce5f Mon Sep 17 00:00:00 2001 From: Nobuhiro Iwamatsu Date: Thu, 23 Mar 2017 08:04:14 +0900 Subject: [PATCH] mtd: spi-nor: Add support for N25Q256A11 Add new Micron N25Q256A (N25Q256A11) 256Mbit NOR Flash in the list of supported devices. This chip has the same structure as the N25Q256A but ID and voltage (1V8) to use is different. Therefore, this adds N25Q256A11 as n25q256ax1. In the future, for new Micron memories we could use the patterns "n25q*ax1" for 1V8 and "n25q*ax3" for 3V3 memories. Signed-off-by: Nobuhiro Iwamatsu Signed-off-by: Cyrille Pitchen --- drivers/mtd/spi-nor/spi-nor.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c index d3cb44b28490..19b0b01be2d3 100644 --- a/drivers/mtd/spi-nor/spi-nor.c +++ b/drivers/mtd/spi-nor/spi-nor.c @@ -1037,6 +1037,7 @@ static const struct flash_info spi_nor_ids[] = { { "n25q128a11", INFO(0x20bb18, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_QUAD_READ) }, { "n25q128a13", INFO(0x20ba18, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_QUAD_READ) }, { "n25q256a", INFO(0x20ba19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ) }, + { "n25q256ax1", INFO(0x20bb19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ) }, { "n25q512a", INFO(0x20bb20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) }, { "n25q512ax3", INFO(0x20ba20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) }, { "n25q00", INFO(0x20ba21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) }, -- 2.20.1