From 811cb897564625f196258f15bab485b9bbdd7a36 Mon Sep 17 00:00:00 2001 From: =?utf8?q?C=C3=A9dric=20Le=20Goater?= Date: Wed, 2 Aug 2017 10:51:51 +0200 Subject: [PATCH] mtd: spi-nor: aspeed: set 4B setting for all chips MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit The driver made the wrong assumption that the 4B setting was autodetected for all chips of the AST2500 FMC flash controller. This is only the case for the CS0. Signed-off-by: Cédric Le Goater Signed-off-by: Cyrille Pitchen --- drivers/mtd/spi-nor/aspeed-smc.c | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-) diff --git a/drivers/mtd/spi-nor/aspeed-smc.c b/drivers/mtd/spi-nor/aspeed-smc.c index 0106357421bd..8d3cbe27efb6 100644 --- a/drivers/mtd/spi-nor/aspeed-smc.c +++ b/drivers/mtd/spi-nor/aspeed-smc.c @@ -621,19 +621,18 @@ static void aspeed_smc_chip_set_type(struct aspeed_smc_chip *chip, int type) } /* - * The AST2500 FMC flash controller should be strapped by hardware, or - * autodetected, but the AST2500 SPI flash needs to be set. + * The first chip of the AST2500 FMC flash controller is strapped by + * hardware, or autodetected, but other chips need to be set. Enforce + * the 4B setting for all chips. */ static void aspeed_smc_chip_set_4b(struct aspeed_smc_chip *chip) { struct aspeed_smc_controller *controller = chip->controller; u32 reg; - if (chip->controller->info == &spi_2500_info) { - reg = readl(controller->regs + CE_CONTROL_REG); - reg |= 1 << chip->cs; - writel(reg, controller->regs + CE_CONTROL_REG); - } + reg = readl(controller->regs + CE_CONTROL_REG); + reg |= 1 << chip->cs; + writel(reg, controller->regs + CE_CONTROL_REG); } /* -- 2.20.1