From 808dc752e590c34db0fc9cdc3c693b433d101f81 Mon Sep 17 00:00:00 2001 From: ChiHun Won Date: Mon, 4 Jun 2018 15:48:52 +0900 Subject: [PATCH] [9610] arm64: dts: add DPU BTS related information. AXI ports of each DPU_DMAs are defined in DPP DT information. And PPC(Pixel Per Clock) value is defined in DECON DT information. Change-Id: I207c975c3bf63fcbf37cdc6d796c917a8024a2e4 Signed-off-by: ChiHun Won --- arch/arm64/boot/dts/exynos/exynos9610.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/exynos9610.dtsi b/arch/arm64/boot/dts/exynos/exynos9610.dtsi index 0008a519998f..6ecec42452fe 100644 --- a/arch/arm64/boot/dts/exynos/exynos9610.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos9610.dtsi @@ -2380,6 +2380,7 @@ /* DPU_DMA IRQ, DPP IRQ */ interrupts = <0 210 0>, <0 214 0>; attr = <0x50087>; /* DPP/IDMA/HDR10/FLIP/BLOCK/AFBC */ + port = <0>; /* AXI port number */ }; dpp_1: dpp@0x14883000 { /* VG0 */ @@ -2388,6 +2389,7 @@ reg = <0x0 0x14883000 0x1000>, <0x0 0x14896000 0x1000>; interrupts = <0 211 0>, <0 215 0>; attr = <0x500B6>; /* DPP/IDMA/HDR10/SCALE/CSC/FLIP/BLOCK */ + port = <0>; /* AXI port number */ }; dpp_2: dpp@0x14881000 { /* G0 */ @@ -2396,6 +2398,7 @@ reg = <0x0 0x14881000 0x1000>, <0x0 0x14891000 0x1000>; interrupts = <0 208 0>, <0 212 0>; attr = <0x50006>; /* DPP/IDMA/FLIP/BLOCK */ + port = <0>; /* AXI port number */ }; dpp_3: dpp@0x14882000 { /* G1 */ @@ -2404,6 +2407,7 @@ reg = <0x0 0x14882000 0x1000>, <0x0 0x14892000 0x1000>; interrupts = <0 209 0>, <0 213 0>; attr = <0x50006>; /* DPP/IDMA/FLIP/BLOCK */ + port = <0>; /* AXI port number */ }; disp_ss: disp_ss@0x14810000 { /* SYSREG_DISPAUD */ @@ -2467,6 +2471,9 @@ /* power domain */ pd_name = "pd-dispaud"; + /* pixel per clock */ + ppc = <1>; + #address-cells = <2>; #size-cells = <1>; ranges; -- 2.20.1