From 7f9c7ded39cc4a985a17b64bc76d0b86ccab3c4b Mon Sep 17 00:00:00 2001 From: Sunmi Lee Date: Tue, 3 Jul 2018 20:13:03 +0900 Subject: [PATCH] [COMMON] fimc-is2: Added new hw-api functions to support djag_wb_thres Implementation of api function for set_djag_wb_thres. PR JIRA ID: CPR-31 Change-Id: Ib3878f929b37e8253b6ee18707e84b24cdc66b60 Signed-off-by: Sunmi Lee --- .../hardware/api/fimc-is-hw-api-mcscaler-v2.h | 1 + .../hardware/api/fimc-is-hw-api-mcscaler-v5_0.c | 12 ++++++++++++ 2 files changed, 13 insertions(+) diff --git a/drivers/media/platform/exynos/fimc-is2/hardware/api/fimc-is-hw-api-mcscaler-v2.h b/drivers/media/platform/exynos/fimc-is2/hardware/api/fimc-is-hw-api-mcscaler-v2.h index 06ee3d14e7cc..0768626d368e 100644 --- a/drivers/media/platform/exynos/fimc-is2/hardware/api/fimc-is-hw-api-mcscaler-v2.h +++ b/drivers/media/platform/exynos/fimc-is2/hardware/api/fimc-is-hw-api-mcscaler-v2.h @@ -225,6 +225,7 @@ void fimc_is_scaler_set_djag_scaling_ratio(void __iomem *base_addr, u32 hratio, void fimc_is_scaler_set_djag_init_phase_offset(void __iomem *base_addr, u32 h_offset, u32 v_offset); void fimc_is_scaler_set_djag_round_mode(void __iomem *base_addr, u32 round_enable); void fimc_is_scaler_set_djag_tunning_param(void __iomem *base_addr, const struct djag_setfile_contents *djag_tune); +void fimc_is_scaler_set_djag_wb_thres(void __iomem *base_addr, struct djag_wb_thres_cfg *djag_wb); /* cac */ void fimc_is_scaler_set_cac_enable(void __iomem *base_addr, u32 en); diff --git a/drivers/media/platform/exynos/fimc-is2/hardware/api/fimc-is-hw-api-mcscaler-v5_0.c b/drivers/media/platform/exynos/fimc-is2/hardware/api/fimc-is-hw-api-mcscaler-v5_0.c index ed166e773f62..0a1c9289df10 100644 --- a/drivers/media/platform/exynos/fimc-is2/hardware/api/fimc-is-hw-api-mcscaler-v5_0.c +++ b/drivers/media/platform/exynos/fimc-is2/hardware/api/fimc-is-hw-api-mcscaler-v5_0.c @@ -3499,6 +3499,18 @@ void fimc_is_scaler_set_djag_tunning_param(void __iomem *base_addr, const struct fimc_is_hw_set_reg(base_addr, &mcsc_regs[MCSC_R_DJAG_CP_ARBI], reg_val); } +void fimc_is_scaler_set_djag_wb_thres(void __iomem *base_addr, struct djag_wb_thres_cfg *djag_wb) +{ + u32 reg_val = 0; + + if (!djag_wb) + return; + + reg_val = fimc_is_hw_set_field_value(reg_val, &mcsc_fields[MCSC_F_DJAG_DITHER_WB_THRES], + djag_wb->dither_wb_thres); + fimc_is_hw_set_reg(base_addr, &mcsc_regs[MCSC_R_DJAG_DITHER_THRES], reg_val); +} + /* for CAC */ void fimc_is_scaler_set_cac_enable(void __iomem *base_addr, u32 en) { -- 2.20.1