From 7db85dd0828803f44f50ed6953f3f7cb762b830d Mon Sep 17 00:00:00 2001 From: Matthew Gerlach Date: Mon, 3 Feb 2014 14:22:59 -0800 Subject: [PATCH] ARM: socfpga: dts: add missing clock gates to socfpga.dtsi The gates for the clocks coming out of the sdram pll were missing. The change adds the missing nodes to the device tree. Signed-off-by: Matthew Gerlach Signed-off-by: Dinh Nguyen --- arch/arm/boot/dts/socfpga.dtsi | 31 ++++++++++++++++++++++++++++++- 1 file changed, 30 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi index b0acaec3b81a..86e0fb6fff9c 100644 --- a/arch/arm/boot/dts/socfpga.dtsi +++ b/arch/arm/boot/dts/socfpga.dtsi @@ -481,8 +481,37 @@ clocks = <&f2s_periph_ref_clk>, <&main_qspi_clk>, <&per_qspi_clk>; clk-gate = <0xa0 11>; }; + + ddr_dqs_clk_gate: ddr_dqs_clk_gate { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&ddr_dqs_clk>; + clk-gate = <0xd8 0>; + }; + + ddr_2x_dqs_clk_gate: ddr_2x_dqs_clk_gate { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&ddr_2x_dqs_clk>; + clk-gate = <0xd8 1>; + }; + + ddr_dq_clk_gate: ddr_dq_clk_gate { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&ddr_dq_clk>; + clk-gate = <0xd8 2>; + }; + + h2f_user2_clk: h2f_user2_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&h2f_usr2_clk>; + clk-gate = <0xd8 3>; + }; + }; - }; + }; gmac0: ethernet@ff700000 { compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac"; -- 2.20.1