From 76e52dd01cabc340c1a58f540c9d6bf0e79c6b23 Mon Sep 17 00:00:00 2001 From: Marc Zyngier Date: Wed, 30 Sep 2015 12:01:16 +0100 Subject: [PATCH] irqchip/gic: Warn if GICv3 system registers are enabled When using a GICv3 in compatibility (v2) mode, having GICv3 system register access enabled is not really compliant with the architecture. Warn if the firmware (or the hypervisor) has been lazy. Reviewed-by: Catalin Marinas Signed-off-by: Marc Zyngier --- drivers/irqchip/irq-gic.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c index d0ce7ed1ac8a..a9f23cfa9c96 100644 --- a/drivers/irqchip/irq-gic.c +++ b/drivers/irqchip/irq-gic.c @@ -51,6 +51,19 @@ #include "irq-gic-common.h" +#ifdef CONFIG_ARM64 +#include + +static void gic_check_cpu_features(void) +{ + WARN_TAINT_ONCE(cpus_have_cap(ARM64_HAS_SYSREG_GIC_CPUIF), + TAINT_CPU_OUT_OF_SPEC, + "GICv3 system registers enabled, broken firmware!\n"); +} +#else +#define gic_check_cpu_features() do { } while(0) +#endif + union gic_base { void __iomem *common_base; void __percpu * __iomem *percpu_base; @@ -987,6 +1000,8 @@ static void __init __gic_init_bases(unsigned int gic_nr, int irq_start, BUG_ON(gic_nr >= MAX_GIC_NR); + gic_check_cpu_features(); + gic = &gic_data[gic_nr]; #ifdef CONFIG_GIC_NON_BANKED if (percpu_offset) { /* Frankein-GIC without banked registers... */ -- 2.20.1