From 7342a72cc40b4cf50013f8230a6b879e2ba5a73e Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Thu, 9 Mar 2017 14:20:49 +0000 Subject: [PATCH] drm/i915: Ignore skl+ for debugfs/i915_sr_status MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit There is no easily digestible single self-refresh status bit, so don't report one for debugfs/i915_sr_status on gen9+. For the moment this avoids a read of the non-existent WM1_LP_ILK register. Signed-off-by: Chris Wilson Cc: Ville Syrjälä Link: http://patchwork.freedesktop.org/patch/msgid/20170309142049.16033-1-chris@chris-wilson.co.uk Reviewed-by: Ville Syrjälä --- drivers/gpu/drm/i915/i915_debugfs.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index fd0aa29e0c3b..115433d46477 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -1749,7 +1749,9 @@ static int i915_sr_status(struct seq_file *m, void *unused) intel_runtime_pm_get(dev_priv); intel_display_power_get(dev_priv, POWER_DOMAIN_INIT); - if (HAS_PCH_SPLIT(dev_priv)) + if (INTEL_GEN(dev_priv) >= 9) + /* no global SR status; inspect per-plane WM */; + else if (HAS_PCH_SPLIT(dev_priv)) sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN; else if (IS_I965GM(dev_priv) || IS_G4X(dev_priv) || IS_I945G(dev_priv) || IS_I945GM(dev_priv)) -- 2.20.1