From 72dd2c54ee630701608c08fd85e0eaf75336e31c Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Thu, 28 Mar 2013 10:46:29 -0400 Subject: [PATCH] drm/radeon/dpm: add dpm_set_power_state failure output (7xx-ni) Signed-off-by: Alex Deucher --- drivers/gpu/drm/radeon/btc_dpm.c | 29 ++++++++++++----- drivers/gpu/drm/radeon/cypress_dpm.c | 26 ++++++++++----- drivers/gpu/drm/radeon/ni_dpm.c | 48 +++++++++++++++++++++------- drivers/gpu/drm/radeon/rv770_dpm.c | 20 +++++++++--- 4 files changed, 90 insertions(+), 33 deletions(-) diff --git a/drivers/gpu/drm/radeon/btc_dpm.c b/drivers/gpu/drm/radeon/btc_dpm.c index 4a50b508d302..0cbf75e07849 100644 --- a/drivers/gpu/drm/radeon/btc_dpm.c +++ b/drivers/gpu/drm/radeon/btc_dpm.c @@ -2274,44 +2274,57 @@ int btc_dpm_set_power_state(struct radeon_device *rdev) ret = btc_disable_ulv(rdev); btc_set_boot_state_timing(rdev); ret = rv770_restrict_performance_levels_before_switch(rdev); - if (ret) + if (ret) { + DRM_ERROR("rv770_restrict_performance_levels_before_switch failed\n"); return ret; + } if (eg_pi->pcie_performance_request) cypress_notify_link_speed_change_before_state_change(rdev, new_ps, old_ps); rv770_set_uvd_clock_before_set_eng_clock(rdev, new_ps, old_ps); ret = rv770_halt_smc(rdev); - if (ret) + if (ret) { + DRM_ERROR("rv770_halt_smc failed\n"); return ret; + } btc_set_at_for_uvd(rdev, new_ps); if (eg_pi->smu_uvd_hs) btc_notify_uvd_to_smc(rdev, new_ps); ret = cypress_upload_sw_state(rdev, new_ps); - if (ret) + if (ret) { + DRM_ERROR("cypress_upload_sw_state failed\n"); return ret; - + } if (eg_pi->dynamic_ac_timing) { ret = cypress_upload_mc_reg_table(rdev, new_ps); - if (ret) + if (ret) { + DRM_ERROR("cypress_upload_mc_reg_table failed\n"); return ret; + } } cypress_program_memory_timing_parameters(rdev, new_ps); ret = rv770_resume_smc(rdev); - if (ret) + if (ret) { + DRM_ERROR("rv770_resume_smc failed\n"); return ret; + } ret = rv770_set_sw_state(rdev); - if (ret) + if (ret) { + DRM_ERROR("rv770_set_sw_state failed\n"); return ret; + } rv770_set_uvd_clock_after_set_eng_clock(rdev, new_ps, old_ps); if (eg_pi->pcie_performance_request) cypress_notify_link_speed_change_after_state_change(rdev, new_ps, old_ps); ret = btc_set_power_state_conditionally_enable_ulv(rdev, new_ps); - if (ret) + if (ret) { + DRM_ERROR("btc_set_power_state_conditionally_enable_ulv failed\n"); return ret; + } #if 0 /* XXX */ diff --git a/drivers/gpu/drm/radeon/cypress_dpm.c b/drivers/gpu/drm/radeon/cypress_dpm.c index f90e5498785c..0097ff725e67 100644 --- a/drivers/gpu/drm/radeon/cypress_dpm.c +++ b/drivers/gpu/drm/radeon/cypress_dpm.c @@ -1971,34 +1971,44 @@ int cypress_dpm_set_power_state(struct radeon_device *rdev) int ret; ret = rv770_restrict_performance_levels_before_switch(rdev); - if (ret) + if (ret) { + DRM_ERROR("rv770_restrict_performance_levels_before_switch failed\n"); return ret; - + } if (eg_pi->pcie_performance_request) cypress_notify_link_speed_change_before_state_change(rdev, new_ps, old_ps); rv770_set_uvd_clock_before_set_eng_clock(rdev, new_ps, old_ps); ret = rv770_halt_smc(rdev); - if (ret) + if (ret) { + DRM_ERROR("rv770_halt_smc failed\n"); return ret; + } ret = cypress_upload_sw_state(rdev, new_ps); - if (ret) + if (ret) { + DRM_ERROR("cypress_upload_sw_state failed\n"); return ret; - + } if (eg_pi->dynamic_ac_timing) { ret = cypress_upload_mc_reg_table(rdev, new_ps); - if (ret) + if (ret) { + DRM_ERROR("cypress_upload_mc_reg_table failed\n"); return ret; + } } cypress_program_memory_timing_parameters(rdev, new_ps); ret = rv770_resume_smc(rdev); - if (ret) + if (ret) { + DRM_ERROR("rv770_resume_smc failed\n"); return ret; + } ret = rv770_set_sw_state(rdev); - if (ret) + if (ret) { + DRM_ERROR("rv770_set_sw_state failed\n"); return ret; + } rv770_set_uvd_clock_after_set_eng_clock(rdev, new_ps, old_ps); if (eg_pi->pcie_performance_request) diff --git a/drivers/gpu/drm/radeon/ni_dpm.c b/drivers/gpu/drm/radeon/ni_dpm.c index 94007e4826a6..a1f128613cf4 100644 --- a/drivers/gpu/drm/radeon/ni_dpm.c +++ b/drivers/gpu/drm/radeon/ni_dpm.c @@ -3726,47 +3726,71 @@ int ni_dpm_set_power_state(struct radeon_device *rdev) int ret; ret = ni_restrict_performance_levels_before_switch(rdev); - if (ret) + if (ret) { + DRM_ERROR("ni_restrict_performance_levels_before_switch failed\n"); return ret; + } rv770_set_uvd_clock_before_set_eng_clock(rdev, new_ps, old_ps); ret = ni_enable_power_containment(rdev, new_ps, false); - if (ret) + if (ret) { + DRM_ERROR("ni_enable_power_containment failed\n"); return ret; + } ret = ni_enable_smc_cac(rdev, new_ps, false); - if (ret) + if (ret) { + DRM_ERROR("ni_enable_smc_cac failed\n"); return ret; + } ret = rv770_halt_smc(rdev); - if (ret) + if (ret) { + DRM_ERROR("rv770_halt_smc failed\n"); return ret; + } if (eg_pi->smu_uvd_hs) btc_notify_uvd_to_smc(rdev, new_ps); ret = ni_upload_sw_state(rdev, new_ps); - if (ret) + if (ret) { + DRM_ERROR("ni_upload_sw_state failed\n"); return ret; + } if (eg_pi->dynamic_ac_timing) { ret = ni_upload_mc_reg_table(rdev, new_ps); - if (ret) + if (ret) { + DRM_ERROR("ni_upload_mc_reg_table failed\n"); return ret; + } } ret = ni_program_memory_timing_parameters(rdev, new_ps); - if (ret) + if (ret) { + DRM_ERROR("ni_program_memory_timing_parameters failed\n"); return ret; + } ret = ni_populate_smc_tdp_limits(rdev, new_ps); - if (ret) + if (ret) { + DRM_ERROR("ni_populate_smc_tdp_limits failed\n"); return ret; + } ret = rv770_resume_smc(rdev); - if (ret) + if (ret) { + DRM_ERROR("rv770_resume_smc failed\n"); return ret; + } ret = rv770_set_sw_state(rdev); - if (ret) + if (ret) { + DRM_ERROR("rv770_set_sw_state failed\n"); return ret; + } rv770_set_uvd_clock_after_set_eng_clock(rdev, new_ps, old_ps); ret = ni_enable_smc_cac(rdev, new_ps, true); - if (ret) + if (ret) { + DRM_ERROR("ni_enable_smc_cac failed\n"); return ret; + } ret = ni_enable_power_containment(rdev, new_ps, true); - if (ret) + if (ret) { + DRM_ERROR("ni_enable_power_containment failed\n"); return ret; + } #if 0 /* XXX */ diff --git a/drivers/gpu/drm/radeon/rv770_dpm.c b/drivers/gpu/drm/radeon/rv770_dpm.c index cdf823d9fae6..d7954e4fb440 100644 --- a/drivers/gpu/drm/radeon/rv770_dpm.c +++ b/drivers/gpu/drm/radeon/rv770_dpm.c @@ -2015,24 +2015,34 @@ int rv770_dpm_set_power_state(struct radeon_device *rdev) int ret; ret = rv770_restrict_performance_levels_before_switch(rdev); - if (ret) + if (ret) { + DRM_ERROR("rv770_restrict_performance_levels_before_switch failed\n"); return ret; + } rv770_set_uvd_clock_before_set_eng_clock(rdev, new_ps, old_ps); ret = rv770_halt_smc(rdev); - if (ret) + if (ret) { + DRM_ERROR("rv770_halt_smc failed\n"); return ret; + } ret = rv770_upload_sw_state(rdev, new_ps); - if (ret) + if (ret) { + DRM_ERROR("rv770_upload_sw_state failed\n"); return ret; + } r7xx_program_memory_timing_parameters(rdev, new_ps); if (pi->dcodt) rv770_program_dcodt_before_state_switch(rdev, new_ps, old_ps); ret = rv770_resume_smc(rdev); - if (ret) + if (ret) { + DRM_ERROR("rv770_resume_smc failed\n"); return ret; + } ret = rv770_set_sw_state(rdev); - if (ret) + if (ret) { + DRM_ERROR("rv770_set_sw_state failed\n"); return ret; + } if (pi->dcodt) rv770_program_dcodt_after_state_switch(rdev, new_ps, old_ps); rv770_set_uvd_clock_after_set_eng_clock(rdev, new_ps, old_ps); -- 2.20.1