From 6f41c7c56929b3a2ad943d5b6dd4d66d716e74d7 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Thu, 20 Aug 2015 14:54:22 +1000 Subject: [PATCH] drm/nouveau/sw: convert to new-style nvkm_engine Signed-off-by: Ben Skeggs --- .../gpu/drm/nouveau/include/nvkm/engine/sw.h | 29 +--- .../gpu/drm/nouveau/nvkm/engine/device/base.c | 136 +++++++++--------- .../drm/nouveau/nvkm/engine/device/gf100.c | 9 -- .../drm/nouveau/nvkm/engine/device/gk104.c | 8 -- .../drm/nouveau/nvkm/engine/device/gm100.c | 4 - .../gpu/drm/nouveau/nvkm/engine/device/nv04.c | 2 - .../gpu/drm/nouveau/nvkm/engine/device/nv10.c | 7 - .../gpu/drm/nouveau/nvkm/engine/device/nv20.c | 4 - .../gpu/drm/nouveau/nvkm/engine/device/nv30.c | 5 - .../gpu/drm/nouveau/nvkm/engine/device/nv40.c | 16 --- .../gpu/drm/nouveau/nvkm/engine/device/nv50.c | 14 -- drivers/gpu/drm/nouveau/nvkm/engine/sw/base.c | 25 ++-- .../gpu/drm/nouveau/nvkm/engine/sw/gf100.c | 18 +-- drivers/gpu/drm/nouveau/nvkm/engine/sw/nv04.c | 35 +---- drivers/gpu/drm/nouveau/nvkm/engine/sw/nv10.c | 29 +--- drivers/gpu/drm/nouveau/nvkm/engine/sw/nv50.c | 39 +---- drivers/gpu/drm/nouveau/nvkm/engine/sw/nv50.h | 15 -- drivers/gpu/drm/nouveau/nvkm/engine/sw/nvsw.c | 9 +- drivers/gpu/drm/nouveau/nvkm/engine/sw/priv.h | 3 + 19 files changed, 115 insertions(+), 292 deletions(-) diff --git a/drivers/gpu/drm/nouveau/include/nvkm/engine/sw.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/sw.h index f2288d468cb6..096e7dbd1e65 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/engine/sw.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/engine/sw.h @@ -3,33 +3,16 @@ #include struct nvkm_sw { - struct nvkm_engine engine; const struct nvkm_sw_func *func; + struct nvkm_engine engine; + struct list_head chan; }; bool nvkm_sw_mthd(struct nvkm_sw *sw, int chid, int subc, u32 mthd, u32 data); -#define nvkm_sw_create(p,e,c,d) \ - nvkm_sw_ctor((p), (e), (c), sizeof(**d), (void **)d) -int -nvkm_sw_ctor(struct nvkm_object *parent, struct nvkm_object *engine, - struct nvkm_oclass *oclass, int length, void **pobject); -#define nvkm_sw_destroy(d) \ - nvkm_engine_destroy(&(d)->engine) -#define nvkm_sw_init(d) \ - nvkm_engine_init_old(&(d)->engine) -#define nvkm_sw_fini(d,s) \ - nvkm_engine_fini_old(&(d)->engine, (s)) - -#define _nvkm_sw_dtor _nvkm_engine_dtor -#define _nvkm_sw_init _nvkm_engine_init -#define _nvkm_sw_fini _nvkm_engine_fini - -extern struct nvkm_oclass *nv04_sw_oclass; -extern struct nvkm_oclass *nv10_sw_oclass; -extern struct nvkm_oclass *nv50_sw_oclass; -extern struct nvkm_oclass *gf100_sw_oclass; - -void nv04_sw_intr(struct nvkm_subdev *); +int nv04_sw_new(struct nvkm_device *, int, struct nvkm_sw **); +int nv10_sw_new(struct nvkm_device *, int, struct nvkm_sw **); +int nv50_sw_new(struct nvkm_device *, int, struct nvkm_sw **); +int gf100_sw_new(struct nvkm_device *, int, struct nvkm_sw **); #endif diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c index c954ae4189a9..302122c059b5 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c @@ -90,7 +90,7 @@ nv4_chipset = { .dma = nv04_dma_new, .fifo = nv04_fifo_new, .gr = nv04_gr_new, -// .sw = nv04_sw_new, + .sw = nv04_sw_new, }; static const struct nvkm_device_chip @@ -110,7 +110,7 @@ nv5_chipset = { .dma = nv04_dma_new, .fifo = nv04_fifo_new, .gr = nv04_gr_new, -// .sw = nv04_sw_new, + .sw = nv04_sw_new, }; static const struct nvkm_device_chip @@ -150,7 +150,7 @@ nv11_chipset = { .dma = nv04_dma_new, .fifo = nv10_fifo_new, .gr = nv15_gr_new, -// .sw = nv10_sw_new, + .sw = nv10_sw_new, }; static const struct nvkm_device_chip @@ -171,7 +171,7 @@ nv15_chipset = { .dma = nv04_dma_new, .fifo = nv10_fifo_new, .gr = nv15_gr_new, -// .sw = nv10_sw_new, + .sw = nv10_sw_new, }; static const struct nvkm_device_chip @@ -192,7 +192,7 @@ nv17_chipset = { .dma = nv04_dma_new, .fifo = nv17_fifo_new, .gr = nv17_gr_new, -// .sw = nv10_sw_new, + .sw = nv10_sw_new, }; static const struct nvkm_device_chip @@ -213,7 +213,7 @@ nv18_chipset = { .dma = nv04_dma_new, .fifo = nv17_fifo_new, .gr = nv17_gr_new, -// .sw = nv10_sw_new, + .sw = nv10_sw_new, }; static const struct nvkm_device_chip @@ -234,7 +234,7 @@ nv1a_chipset = { .dma = nv04_dma_new, .fifo = nv10_fifo_new, .gr = nv15_gr_new, -// .sw = nv10_sw_new, + .sw = nv10_sw_new, }; static const struct nvkm_device_chip @@ -255,7 +255,7 @@ nv1f_chipset = { .dma = nv04_dma_new, .fifo = nv17_fifo_new, .gr = nv17_gr_new, -// .sw = nv10_sw_new, + .sw = nv10_sw_new, }; static const struct nvkm_device_chip @@ -276,7 +276,7 @@ nv20_chipset = { .dma = nv04_dma_new, .fifo = nv17_fifo_new, .gr = nv20_gr_new, -// .sw = nv10_sw_new, + .sw = nv10_sw_new, }; static const struct nvkm_device_chip @@ -297,7 +297,7 @@ nv25_chipset = { .dma = nv04_dma_new, .fifo = nv17_fifo_new, .gr = nv25_gr_new, -// .sw = nv10_sw_new, + .sw = nv10_sw_new, }; static const struct nvkm_device_chip @@ -318,7 +318,7 @@ nv28_chipset = { .dma = nv04_dma_new, .fifo = nv17_fifo_new, .gr = nv25_gr_new, -// .sw = nv10_sw_new, + .sw = nv10_sw_new, }; static const struct nvkm_device_chip @@ -339,7 +339,7 @@ nv2a_chipset = { .dma = nv04_dma_new, .fifo = nv17_fifo_new, .gr = nv2a_gr_new, -// .sw = nv10_sw_new, + .sw = nv10_sw_new, }; static const struct nvkm_device_chip @@ -360,7 +360,7 @@ nv30_chipset = { .dma = nv04_dma_new, .fifo = nv17_fifo_new, .gr = nv30_gr_new, -// .sw = nv10_sw_new, + .sw = nv10_sw_new, }; static const struct nvkm_device_chip @@ -382,7 +382,7 @@ nv31_chipset = { .fifo = nv17_fifo_new, .gr = nv30_gr_new, // .mpeg = nv31_mpeg_new, -// .sw = nv10_sw_new, + .sw = nv10_sw_new, }; static const struct nvkm_device_chip @@ -404,7 +404,7 @@ nv34_chipset = { .fifo = nv17_fifo_new, .gr = nv34_gr_new, // .mpeg = nv31_mpeg_new, -// .sw = nv10_sw_new, + .sw = nv10_sw_new, }; static const struct nvkm_device_chip @@ -425,7 +425,7 @@ nv35_chipset = { .dma = nv04_dma_new, .fifo = nv17_fifo_new, .gr = nv35_gr_new, -// .sw = nv10_sw_new, + .sw = nv10_sw_new, }; static const struct nvkm_device_chip @@ -447,7 +447,7 @@ nv36_chipset = { .fifo = nv17_fifo_new, .gr = nv35_gr_new, // .mpeg = nv31_mpeg_new, -// .sw = nv10_sw_new, + .sw = nv10_sw_new, }; static const struct nvkm_device_chip @@ -472,7 +472,7 @@ nv40_chipset = { .gr = nv40_gr_new, // .mpeg = nv40_mpeg_new, .pm = nv40_pm_new, -// .sw = nv10_sw_new, + .sw = nv10_sw_new, }; static const struct nvkm_device_chip @@ -497,7 +497,7 @@ nv41_chipset = { .gr = nv40_gr_new, // .mpeg = nv40_mpeg_new, .pm = nv40_pm_new, -// .sw = nv10_sw_new, + .sw = nv10_sw_new, }; static const struct nvkm_device_chip @@ -522,7 +522,7 @@ nv42_chipset = { .gr = nv40_gr_new, // .mpeg = nv40_mpeg_new, .pm = nv40_pm_new, -// .sw = nv10_sw_new, + .sw = nv10_sw_new, }; static const struct nvkm_device_chip @@ -547,7 +547,7 @@ nv43_chipset = { .gr = nv40_gr_new, // .mpeg = nv40_mpeg_new, .pm = nv40_pm_new, -// .sw = nv10_sw_new, + .sw = nv10_sw_new, }; static const struct nvkm_device_chip @@ -572,7 +572,7 @@ nv44_chipset = { .gr = nv44_gr_new, // .mpeg = nv44_mpeg_new, .pm = nv40_pm_new, -// .sw = nv10_sw_new, + .sw = nv10_sw_new, }; static const struct nvkm_device_chip @@ -597,7 +597,7 @@ nv45_chipset = { .gr = nv40_gr_new, // .mpeg = nv44_mpeg_new, .pm = nv40_pm_new, -// .sw = nv10_sw_new, + .sw = nv10_sw_new, }; static const struct nvkm_device_chip @@ -622,7 +622,7 @@ nv46_chipset = { .gr = nv44_gr_new, // .mpeg = nv44_mpeg_new, .pm = nv40_pm_new, -// .sw = nv10_sw_new, + .sw = nv10_sw_new, }; static const struct nvkm_device_chip @@ -647,7 +647,7 @@ nv47_chipset = { .gr = nv40_gr_new, // .mpeg = nv44_mpeg_new, .pm = nv40_pm_new, -// .sw = nv10_sw_new, + .sw = nv10_sw_new, }; static const struct nvkm_device_chip @@ -672,7 +672,7 @@ nv49_chipset = { .gr = nv40_gr_new, // .mpeg = nv44_mpeg_new, .pm = nv40_pm_new, -// .sw = nv10_sw_new, + .sw = nv10_sw_new, }; static const struct nvkm_device_chip @@ -697,7 +697,7 @@ nv4a_chipset = { .gr = nv44_gr_new, // .mpeg = nv44_mpeg_new, .pm = nv40_pm_new, -// .sw = nv10_sw_new, + .sw = nv10_sw_new, }; static const struct nvkm_device_chip @@ -722,7 +722,7 @@ nv4b_chipset = { .gr = nv40_gr_new, // .mpeg = nv44_mpeg_new, .pm = nv40_pm_new, -// .sw = nv10_sw_new, + .sw = nv10_sw_new, }; static const struct nvkm_device_chip @@ -747,7 +747,7 @@ nv4c_chipset = { .gr = nv44_gr_new, // .mpeg = nv44_mpeg_new, .pm = nv40_pm_new, -// .sw = nv10_sw_new, + .sw = nv10_sw_new, }; static const struct nvkm_device_chip @@ -772,7 +772,7 @@ nv4e_chipset = { .gr = nv44_gr_new, // .mpeg = nv44_mpeg_new, .pm = nv40_pm_new, -// .sw = nv10_sw_new, + .sw = nv10_sw_new, }; static const struct nvkm_device_chip @@ -800,7 +800,7 @@ nv50_chipset = { .gr = nv50_gr_new, // .mpeg = nv50_mpeg_new, .pm = nv50_pm_new, -// .sw = nv50_sw_new, + .sw = nv50_sw_new, }; static const struct nvkm_device_chip @@ -825,7 +825,7 @@ nv63_chipset = { .gr = nv44_gr_new, // .mpeg = nv44_mpeg_new, .pm = nv40_pm_new, -// .sw = nv10_sw_new, + .sw = nv10_sw_new, }; static const struct nvkm_device_chip @@ -850,7 +850,7 @@ nv67_chipset = { .gr = nv44_gr_new, // .mpeg = nv44_mpeg_new, .pm = nv40_pm_new, -// .sw = nv10_sw_new, + .sw = nv10_sw_new, }; static const struct nvkm_device_chip @@ -875,7 +875,7 @@ nv68_chipset = { .gr = nv44_gr_new, // .mpeg = nv44_mpeg_new, .pm = nv40_pm_new, -// .sw = nv10_sw_new, + .sw = nv10_sw_new, }; static const struct nvkm_device_chip @@ -905,7 +905,7 @@ nv84_chipset = { .gr = g84_gr_new, // .mpeg = g84_mpeg_new, .pm = g84_pm_new, -// .sw = nv50_sw_new, + .sw = nv50_sw_new, .vp = g84_vp_new, }; @@ -936,7 +936,7 @@ nv86_chipset = { .gr = g84_gr_new, // .mpeg = g84_mpeg_new, .pm = g84_pm_new, -// .sw = nv50_sw_new, + .sw = nv50_sw_new, .vp = g84_vp_new, }; @@ -967,7 +967,7 @@ nv92_chipset = { .gr = g84_gr_new, // .mpeg = g84_mpeg_new, .pm = g84_pm_new, -// .sw = nv50_sw_new, + .sw = nv50_sw_new, .vp = g84_vp_new, }; @@ -998,7 +998,7 @@ nv94_chipset = { .gr = g84_gr_new, // .mpeg = g84_mpeg_new, .pm = g84_pm_new, -// .sw = nv50_sw_new, + .sw = nv50_sw_new, .vp = g84_vp_new, }; @@ -1023,8 +1023,8 @@ nv96_chipset = { .volt = nv40_volt_new, .dma = nv50_dma_new, .fifo = g84_fifo_new, -// .sw = nv50_sw_new, .gr = g84_gr_new, + .gr = nv50_gr_new, // .mpeg = g84_mpeg_new, .vp = g84_vp_new, .cipher = g84_cipher_new, @@ -1054,8 +1054,8 @@ nv98_chipset = { .volt = nv40_volt_new, .dma = nv50_dma_new, .fifo = g84_fifo_new, -// .sw = nv50_sw_new, .gr = g84_gr_new, + .sw = nv50_sw_new, .mspdec = g98_mspdec_new, .sec = g98_sec_new, .msvld = g98_msvld_new, @@ -1091,7 +1091,7 @@ nva0_chipset = { .gr = gt200_gr_new, // .mpeg = g84_mpeg_new, .pm = gt200_pm_new, -// .sw = nv50_sw_new, + .sw = nv50_sw_new, .vp = g84_vp_new, }; @@ -1125,7 +1125,7 @@ nva3_chipset = { .msppp = gt215_msppp_new, .msvld = gt215_msvld_new, .pm = gt215_pm_new, -// .sw = nv50_sw_new, + .sw = nv50_sw_new, }; static const struct nvkm_device_chip @@ -1157,7 +1157,7 @@ nva5_chipset = { .msppp = gt215_msppp_new, .msvld = gt215_msvld_new, .pm = gt215_pm_new, -// .sw = nv50_sw_new, + .sw = nv50_sw_new, }; static const struct nvkm_device_chip @@ -1189,7 +1189,7 @@ nva8_chipset = { .msppp = gt215_msppp_new, .msvld = gt215_msvld_new, .pm = gt215_pm_new, -// .sw = nv50_sw_new, + .sw = nv50_sw_new, }; static const struct nvkm_device_chip @@ -1220,7 +1220,7 @@ nvaa_chipset = { .msvld = g98_msvld_new, .pm = g84_pm_new, .sec = g98_sec_new, -// .sw = nv50_sw_new, + .sw = nv50_sw_new, }; static const struct nvkm_device_chip @@ -1251,7 +1251,7 @@ nvac_chipset = { .msvld = g98_msvld_new, .pm = g84_pm_new, .sec = g98_sec_new, -// .sw = nv50_sw_new, + .sw = nv50_sw_new, }; static const struct nvkm_device_chip @@ -1283,7 +1283,7 @@ nvaf_chipset = { .msppp = gt215_msppp_new, .msvld = mcp89_msvld_new, .pm = gt215_pm_new, -// .sw = nv50_sw_new, + .sw = nv50_sw_new, }; static const struct nvkm_device_chip @@ -1318,7 +1318,7 @@ nvc0_chipset = { .msppp = gf100_msppp_new, .msvld = gf100_msvld_new, .pm = gf100_pm_new, -// .sw = gf100_sw_new, + .sw = gf100_sw_new, }; static const struct nvkm_device_chip @@ -1352,7 +1352,7 @@ nvc1_chipset = { .msppp = gf100_msppp_new, .msvld = gf100_msvld_new, .pm = gf108_pm_new, -// .sw = gf100_sw_new, + .sw = gf100_sw_new, }; static const struct nvkm_device_chip @@ -1386,7 +1386,7 @@ nvc3_chipset = { .msppp = gf100_msppp_new, .msvld = gf100_msvld_new, .pm = gf100_pm_new, -// .sw = gf100_sw_new, + .sw = gf100_sw_new, }; static const struct nvkm_device_chip @@ -1421,7 +1421,7 @@ nvc4_chipset = { .msppp = gf100_msppp_new, .msvld = gf100_msvld_new, .pm = gf100_pm_new, -// .sw = gf100_sw_new, + .sw = gf100_sw_new, }; static const struct nvkm_device_chip @@ -1456,7 +1456,7 @@ nvc8_chipset = { .msppp = gf100_msppp_new, .msvld = gf100_msvld_new, .pm = gf100_pm_new, -// .sw = gf100_sw_new, + .sw = gf100_sw_new, }; static const struct nvkm_device_chip @@ -1491,7 +1491,7 @@ nvce_chipset = { .msppp = gf100_msppp_new, .msvld = gf100_msvld_new, .pm = gf100_pm_new, -// .sw = gf100_sw_new, + .sw = gf100_sw_new, }; static const struct nvkm_device_chip @@ -1525,7 +1525,7 @@ nvcf_chipset = { .msppp = gf100_msppp_new, .msvld = gf100_msvld_new, .pm = gf100_pm_new, -// .sw = gf100_sw_new, + .sw = gf100_sw_new, }; static const struct nvkm_device_chip @@ -1557,7 +1557,7 @@ nvd7_chipset = { .msppp = gf100_msppp_new, .msvld = gf100_msvld_new, .pm = gf117_pm_new, -// .sw = gf100_sw_new, + .sw = gf100_sw_new, }; static const struct nvkm_device_chip @@ -1591,7 +1591,7 @@ nvd9_chipset = { .msppp = gf100_msppp_new, .msvld = gf100_msvld_new, .pm = gf117_pm_new, -// .sw = gf100_sw_new, + .sw = gf100_sw_new, }; static const struct nvkm_device_chip @@ -1627,7 +1627,7 @@ nve4_chipset = { .msppp = gf100_msppp_new, .msvld = gk104_msvld_new, .pm = gk104_pm_new, -// .sw = gf100_sw_new, + .sw = gf100_sw_new, }; static const struct nvkm_device_chip @@ -1663,7 +1663,7 @@ nve6_chipset = { .msppp = gf100_msppp_new, .msvld = gk104_msvld_new, .pm = gk104_pm_new, -// .sw = gf100_sw_new, + .sw = gf100_sw_new, }; static const struct nvkm_device_chip @@ -1699,7 +1699,7 @@ nve7_chipset = { .msppp = gf100_msppp_new, .msvld = gk104_msvld_new, .pm = gk104_pm_new, -// .sw = gf100_sw_new, + .sw = gf100_sw_new, }; static const struct nvkm_device_chip @@ -1723,7 +1723,7 @@ nvea_chipset = { .fifo = gk20a_fifo_new, .gr = gk20a_gr_new, .pm = gk104_pm_new, -// .sw = gf100_sw_new, + .sw = gf100_sw_new, }; static const struct nvkm_device_chip @@ -1758,7 +1758,7 @@ nvf0_chipset = { .mspdec = gk104_mspdec_new, .msppp = gf100_msppp_new, .msvld = gk104_msvld_new, -// .sw = gf100_sw_new, + .sw = gf100_sw_new, }; static const struct nvkm_device_chip @@ -1793,7 +1793,7 @@ nvf1_chipset = { .mspdec = gk104_mspdec_new, .msppp = gf100_msppp_new, .msvld = gk104_msvld_new, -// .sw = gf100_sw_new, + .sw = gf100_sw_new, }; static const struct nvkm_device_chip @@ -1828,7 +1828,7 @@ nv106_chipset = { .mspdec = gk104_mspdec_new, .msppp = gf100_msppp_new, .msvld = gk104_msvld_new, -// .sw = gf100_sw_new, + .sw = gf100_sw_new, }; static const struct nvkm_device_chip @@ -1863,7 +1863,7 @@ nv108_chipset = { .mspdec = gk104_mspdec_new, .msppp = gf100_msppp_new, .msvld = gk104_msvld_new, -// .sw = gf100_sw_new, + .sw = gf100_sw_new, }; static const struct nvkm_device_chip @@ -1893,7 +1893,7 @@ nv117_chipset = { .dma = gf119_dma_new, .fifo = gk208_fifo_new, .gr = gm107_gr_new, -// .sw = gf100_sw_new, + .sw = gf100_sw_new, }; static const struct nvkm_device_chip @@ -1922,7 +1922,7 @@ nv124_chipset = { .dma = gf119_dma_new, .fifo = gm204_fifo_new, .gr = gm204_gr_new, -// .sw = gf100_sw_new, + .sw = gf100_sw_new, }; static const struct nvkm_device_chip @@ -1951,7 +1951,7 @@ nv126_chipset = { .dma = gf119_dma_new, .fifo = gm204_fifo_new, .gr = gm206_gr_new, -// .sw = gf100_sw_new, + .sw = gf100_sw_new, }; static const struct nvkm_device_chip @@ -1972,7 +1972,7 @@ nv12b_chipset = { .dma = gf119_dma_new, .fifo = gm20b_fifo_new, .gr = gm20b_gr_new, -// .sw = gf100_sw_new, + .sw = gf100_sw_new, }; #include diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/gf100.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/gf100.c index 67faff5d0b52..3c618162923d 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/gf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/gf100.c @@ -28,31 +28,22 @@ gf100_identify(struct nvkm_device *device) { switch (device->chipset) { case 0xc0: - device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; break; case 0xc4: - device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; break; case 0xc3: - device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; break; case 0xce: - device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; break; case 0xcf: - device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; break; case 0xc1: - device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; break; case 0xc8: - device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; break; case 0xd9: - device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; break; case 0xd7: - device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; break; default: return -EINVAL; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/gk104.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/gk104.c index 3841dc0ac01b..447659718709 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/gk104.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/gk104.c @@ -28,28 +28,20 @@ gk104_identify(struct nvkm_device *device) { switch (device->chipset) { case 0xe4: - device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; break; case 0xe7: - device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; break; case 0xe6: - device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; break; case 0xea: - device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; break; case 0xf0: - device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; break; case 0xf1: - device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; break; case 0x106: - device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; break; case 0x108: - device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; break; default: return -EINVAL; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c index 71e088abb620..e0a214c0cb6e 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c @@ -31,7 +31,6 @@ gm100_identify(struct nvkm_device *device) #if 0 #endif - device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; #if 0 #endif #if 0 @@ -44,7 +43,6 @@ gm100_identify(struct nvkm_device *device) #endif #if 0 #endif - device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; #if 0 #endif break; @@ -55,13 +53,11 @@ gm100_identify(struct nvkm_device *device) #endif #if 0 #endif - device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; #if 0 #endif break; case 0x12b: - device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; break; default: return -EINVAL; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv04.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv04.c index 7a8071be7ed0..369992ba9c36 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv04.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv04.c @@ -28,10 +28,8 @@ nv04_identify(struct nvkm_device *device) { switch (device->chipset) { case 0x04: - device->oclass[NVDEV_ENGINE_SW ] = nv04_sw_oclass; break; case 0x05: - device->oclass[NVDEV_ENGINE_SW ] = nv04_sw_oclass; break; default: return -EINVAL; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv10.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv10.c index 15dbd71ebabf..233f9f9cfda9 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv10.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv10.c @@ -30,25 +30,18 @@ nv10_identify(struct nvkm_device *device) case 0x10: break; case 0x15: - device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; break; case 0x16: - device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; break; case 0x1a: - device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; break; case 0x11: - device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; break; case 0x17: - device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; break; case 0x1f: - device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; break; case 0x18: - device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; break; default: return -EINVAL; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv20.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv20.c index 158efa44054f..d6204a954cba 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv20.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv20.c @@ -28,16 +28,12 @@ nv20_identify(struct nvkm_device *device) { switch (device->chipset) { case 0x20: - device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; break; case 0x25: - device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; break; case 0x28: - device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; break; case 0x2a: - device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; break; default: return -EINVAL; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv30.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv30.c index 5a8fd485467a..5fc9f1751801 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv30.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv30.c @@ -28,21 +28,16 @@ nv30_identify(struct nvkm_device *device) { switch (device->chipset) { case 0x30: - device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; break; case 0x35: - device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; break; case 0x31: - device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv31_mpeg_oclass; break; case 0x36: - device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv31_mpeg_oclass; break; case 0x34: - device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv31_mpeg_oclass; break; default: diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv40.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv40.c index 08c015b0e5a1..cd6c836801cb 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv40.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv40.c @@ -28,67 +28,51 @@ nv40_identify(struct nvkm_device *device) { switch (device->chipset) { case 0x40: - device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass; break; case 0x41: - device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass; break; case 0x42: - device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass; break; case 0x43: - device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass; break; case 0x45: - device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; break; case 0x47: - device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; break; case 0x49: - device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; break; case 0x4b: - device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; break; case 0x44: - device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; break; case 0x46: - device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; break; case 0x4a: - device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; break; case 0x4c: - device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; break; case 0x4e: - device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; break; case 0x63: - device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; break; case 0x67: - device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; break; case 0x68: - device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; break; default: diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c index c285f61ffd8f..2e4592799177 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c @@ -28,54 +28,40 @@ nv50_identify(struct nvkm_device *device) { switch (device->chipset) { case 0x50: - device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv50_mpeg_oclass; break; case 0x84: - device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass; break; case 0x86: - device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass; break; case 0x92: - device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass; break; case 0x94: - device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass; break; case 0x96: - device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass; break; case 0x98: - device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; break; case 0xa0: - device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass; break; case 0xaa: - device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; break; case 0xac: - device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; break; case 0xa3: - device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass; break; case 0xa5: - device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; break; case 0xa8: - device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; break; case 0xaf: - device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; break; default: return -EINVAL; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/sw/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/sw/base.c index efc18787490c..53c1f7e75b54 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/sw/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/sw/base.c @@ -82,26 +82,29 @@ nvkm_sw_cclass_get(struct nvkm_fifo_chan *fifoch, return sw->func->chan_new(sw, fifoch, oclass, pobject); } +static void * +nvkm_sw_dtor(struct nvkm_engine *engine) +{ + return nvkm_sw(engine); +} + static const struct nvkm_engine_func nvkm_sw = { + .dtor = nvkm_sw_dtor, .fifo.cclass = nvkm_sw_cclass_get, .fifo.sclass = nvkm_sw_oclass_get, }; int -nvkm_sw_ctor(struct nvkm_object *parent, struct nvkm_object *engine, - struct nvkm_oclass *oclass, int length, void **pobject) +nvkm_sw_new_(const struct nvkm_sw_func *func, struct nvkm_device *device, + int index, struct nvkm_sw **psw) { struct nvkm_sw *sw; - int ret; - ret = nvkm_engine_create_(parent, engine, oclass, true, "sw", - "sw", length, pobject); - sw = *pobject; - if (ret) - return ret; - - sw->engine.func = &nvkm_sw; + if (!(sw = *psw = kzalloc(sizeof(*sw), GFP_KERNEL))) + return -ENOMEM; INIT_LIST_HEAD(&sw->chan); - return 0; + sw->func = func; + + return nvkm_engine_ctor(&nvkm_sw, device, index, 0, true, &sw->engine); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/sw/gf100.c b/drivers/gpu/drm/nouveau/nvkm/engine/sw/gf100.c index 5cd7844f1d5f..b01ef7eca906 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/sw/gf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/sw/gf100.c @@ -140,7 +140,7 @@ gf100_sw_chan_new(struct nvkm_sw *sw, struct nvkm_fifo_chan *fifoch, ******************************************************************************/ static const struct nvkm_sw_func -gf100_sw_func = { +gf100_sw = { .chan_new = gf100_sw_chan_new, .sclass = { { nvkm_nvsw_new, { -1, -1, NVIF_IOCTL_NEW_V0_SW_GF100 } }, @@ -148,14 +148,8 @@ gf100_sw_func = { } }; -struct nvkm_oclass * -gf100_sw_oclass = &(struct nv50_sw_oclass) { - .base.handle = NV_ENGINE(SW, 0xc0), - .base.ofuncs = &(struct nvkm_ofuncs) { - .ctor = nv50_sw_ctor, - .dtor = _nvkm_sw_dtor, - .init = _nvkm_sw_init, - .fini = _nvkm_sw_fini, - }, - .func = &gf100_sw_func, -}.base; +int +gf100_sw_new(struct nvkm_device *device, int index, struct nvkm_sw **psw) +{ + return nvkm_sw_new_(&gf100_sw, device, index, psw); +} diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/sw/nv04.c b/drivers/gpu/drm/nouveau/nvkm/engine/sw/nv04.c index d8d9d48b66d2..445217ffa791 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/sw/nv04.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/sw/nv04.c @@ -122,12 +122,6 @@ nv04_sw_chan_new(struct nvkm_sw *sw, struct nvkm_fifo_chan *fifo, * software engine/subdev functions ******************************************************************************/ -void -nv04_sw_intr(struct nvkm_subdev *subdev) -{ - nvkm_mask(subdev->device, 0x000100, 0x80000000, 0x00000000); -} - static const struct nvkm_sw_func nv04_sw = { .chan_new = nv04_sw_chan_new, @@ -137,31 +131,8 @@ nv04_sw = { } }; -static int -nv04_sw_ctor(struct nvkm_object *parent, struct nvkm_object *engine, - struct nvkm_oclass *oclass, void *data, u32 size, - struct nvkm_object **pobject) +int +nv04_sw_new(struct nvkm_device *device, int index, struct nvkm_sw **psw) { - struct nvkm_sw *sw; - int ret; - - ret = nvkm_sw_create(parent, engine, oclass, &sw); - *pobject = nv_object(sw); - if (ret) - return ret; - - sw->func = &nv04_sw; - nv_subdev(sw)->intr = nv04_sw_intr; - return 0; + return nvkm_sw_new_(&nv04_sw, device, index, psw); } - -struct nvkm_oclass * -nv04_sw_oclass = &(struct nvkm_oclass) { - .handle = NV_ENGINE(SW, 0x04), - .ofuncs = &(struct nvkm_ofuncs) { - .ctor = nv04_sw_ctor, - .dtor = _nvkm_sw_dtor, - .init = _nvkm_sw_init, - .fini = _nvkm_sw_fini, - }, -}; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/sw/nv10.c b/drivers/gpu/drm/nouveau/nvkm/engine/sw/nv10.c index 1b9fc1b1f69e..adf70d92b244 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/sw/nv10.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/sw/nv10.c @@ -61,31 +61,8 @@ nv10_sw = { } }; -static int -nv10_sw_ctor(struct nvkm_object *parent, struct nvkm_object *engine, - struct nvkm_oclass *oclass, void *data, u32 size, - struct nvkm_object **pobject) +int +nv10_sw_new(struct nvkm_device *device, int index, struct nvkm_sw **psw) { - struct nvkm_sw *sw; - int ret; - - ret = nvkm_sw_create(parent, engine, oclass, &sw); - *pobject = nv_object(sw); - if (ret) - return ret; - - sw->func = &nv10_sw; - nv_subdev(sw)->intr = nv04_sw_intr; - return 0; + return nvkm_sw_new_(&nv10_sw, device, index, psw); } - -struct nvkm_oclass * -nv10_sw_oclass = &(struct nvkm_oclass) { - .handle = NV_ENGINE(SW, 0x10), - .ofuncs = &(struct nvkm_ofuncs) { - .ctor = nv10_sw_ctor, - .dtor = _nvkm_sw_dtor, - .init = _nvkm_sw_init, - .fini = _nvkm_sw_fini, - }, -}; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/sw/nv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/sw/nv50.c index a00d9a55e53b..ef36ba18bff8 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/sw/nv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/sw/nv50.c @@ -48,7 +48,7 @@ nv50_sw_chan_vblsem_release(struct nvkm_notify *notify) nvkm_wr32(device, 0x001710, 0x80000000 | chan->vblank.ctxdma); nvkm_bar_flush(device->bar); - if (nv_device(sw)->chipset == 0x50) { + if (device->chipset == 0x50) { nvkm_wr32(device, 0x001570, chan->vblank.offset); nvkm_wr32(device, 0x001574, chan->vblank.value); } else { @@ -133,27 +133,8 @@ nv50_sw_chan_new(struct nvkm_sw *sw, struct nvkm_fifo_chan *fifoch, * software engine/subdev functions ******************************************************************************/ -int -nv50_sw_ctor(struct nvkm_object *parent, struct nvkm_object *engine, - struct nvkm_oclass *oclass, void *data, u32 size, - struct nvkm_object **pobject) -{ - struct nv50_sw_oclass *pclass = (void *)oclass; - struct nvkm_sw *sw; - int ret; - - ret = nvkm_sw_create(parent, engine, oclass, &sw); - *pobject = nv_object(sw); - if (ret) - return ret; - - sw->func = pclass->func; - nv_subdev(sw)->intr = nv04_sw_intr; - return 0; -} - static const struct nvkm_sw_func -nv50_sw_func = { +nv50_sw = { .chan_new = nv50_sw_chan_new, .sclass = { { nvkm_nvsw_new, { -1, -1, NVIF_IOCTL_NEW_V0_SW_NV50 } }, @@ -161,14 +142,8 @@ nv50_sw_func = { } }; -struct nvkm_oclass * -nv50_sw_oclass = &(struct nv50_sw_oclass) { - .base.handle = NV_ENGINE(SW, 0x50), - .base.ofuncs = &(struct nvkm_ofuncs) { - .ctor = nv50_sw_ctor, - .dtor = _nvkm_sw_dtor, - .init = _nvkm_sw_init, - .fini = _nvkm_sw_fini, - }, - .func = &nv50_sw_func, -}.base; +int +nv50_sw_new(struct nvkm_device *device, int index, struct nvkm_sw **psw) +{ + return nvkm_sw_new_(&nv50_sw, device, index, psw); +} diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/sw/nv50.h b/drivers/gpu/drm/nouveau/nvkm/engine/sw/nv50.h index c90a470564e2..25cdfdef2d46 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/sw/nv50.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/sw/nv50.h @@ -6,21 +6,6 @@ #include "nvsw.h" #include -struct nv50_sw_oclass { - struct nvkm_oclass base; - const struct nvkm_sw_func *func; -}; - -int nv50_sw_ctor(struct nvkm_object *, struct nvkm_object *, - struct nvkm_oclass *, void *, u32, - struct nvkm_object **); - -struct nv50_sw_cclass { - struct nvkm_oclass base; - int (*vblank)(struct nvkm_notify *); - const struct nvkm_sw_chan_func *chan; -}; - struct nv50_sw_chan { struct nvkm_sw_chan base; struct { diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/sw/nvsw.c b/drivers/gpu/drm/nouveau/nvkm/engine/sw/nvsw.c index 6652a9196753..66cf986b9572 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/sw/nvsw.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/sw/nvsw.c @@ -27,18 +27,19 @@ #include static int -nvkm_nvsw_mthd_(struct nvkm_object *base, u32 mthd, void *data, u32 size) +nvkm_nvsw_mthd_(struct nvkm_object *object, u32 mthd, void *data, u32 size) { - struct nvkm_nvsw *nvsw = nvkm_nvsw(base); + struct nvkm_nvsw *nvsw = nvkm_nvsw(object); if (nvsw->func->mthd) return nvsw->func->mthd(nvsw, mthd, data, size); return -ENODEV; } static int -nvkm_nvsw_ntfy_(struct nvkm_object *base, u32 mthd, struct nvkm_event **pevent) +nvkm_nvsw_ntfy_(struct nvkm_object *object, u32 mthd, + struct nvkm_event **pevent) { - struct nvkm_nvsw *nvsw = nvkm_nvsw(base); + struct nvkm_nvsw *nvsw = nvkm_nvsw(object); switch (mthd) { case NVSW_NTFY_UEVENT: *pevent = &nvsw->chan->event; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/sw/priv.h b/drivers/gpu/drm/nouveau/nvkm/engine/sw/priv.h index ae610a32ef5a..0ef1318dc2fd 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/sw/priv.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/sw/priv.h @@ -4,6 +4,9 @@ #include struct nvkm_sw_chan; +int nvkm_sw_new_(const struct nvkm_sw_func *, struct nvkm_device *, + int index, struct nvkm_sw **); + struct nvkm_sw_chan_sclass { int (*ctor)(struct nvkm_sw_chan *, const struct nvkm_oclass *, void *data, u32 size, struct nvkm_object **); -- 2.20.1