From 6e7f8b8e47ae581639c9c1c379bfb2e95c199842 Mon Sep 17 00:00:00 2001 From: Leonid Yegoshin Date: Thu, 14 Nov 2013 16:12:25 +0000 Subject: [PATCH] MIPS: tlb: Set the EHINV bit for TLBINVF cores when invalidating the TLB For MIPS32R3 supported cores, the EHINV bit needs to be set when invalidating the TLB. This is necessary because the legacy software method of representing an invalid TLB entry using an unmapped address value is not guaranteed to work. Signed-off-by: Leonid Yegoshin Signed-off-by: Markos Chandras Signed-off-by: John Crispin Patchwork: http://patchwork.linux-mips.org/patch/6132/ --- arch/mips/include/asm/tlb.h | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/mips/include/asm/tlb.h b/arch/mips/include/asm/tlb.h index 235367cec4e6..4a2349302b55 100644 --- a/arch/mips/include/asm/tlb.h +++ b/arch/mips/include/asm/tlb.h @@ -18,7 +18,9 @@ */ #define tlb_flush(tlb) flush_tlb_mm((tlb)->mm) -#define UNIQUE_ENTRYHI(idx) (CKSEG0 + ((idx) << (PAGE_SHIFT + 1))) +#define UNIQUE_ENTRYHI(idx) \ + ((CKSEG0 + ((idx) << (PAGE_SHIFT + 1))) | \ + (cpu_has_tlbinv ? MIPS_ENTRYHI_EHINV : 0)) #include -- 2.20.1