From 6c70faf1b5d32eb7fa868f1730c51698b53ac677 Mon Sep 17 00:00:00 2001 From: Sean Paul Date: Thu, 20 Jul 2017 16:09:14 -0400 Subject: [PATCH] drm: Fix warning when building docs for scdc_helper Fixes: ../drivers/gpu/drm/drm_scdc_helper.c:203: ERROR: Unexpected indentation. ../drivers/gpu/drm/drm_scdc_helper.c:204: WARNING: Block quote ends without a blank line; unexpected unindent. Changes in v2: - Property blockquote TMDS calculations so they look pretty (Daniel) - Remove duplicate documentation from the header file Signed-off-by: Sean Paul Reviewed-by: Shashank Sharma Signed-off-by: Thierry Reding Link: https://patchwork.freedesktop.org/patch/msgid/20170720200921.36897-1-seanpaul@chromium.org --- drivers/gpu/drm/drm_scdc_helper.c | 33 +++++++++++++++++++------------ include/drm/drm_scdc_helper.h | 25 ----------------------- 2 files changed, 20 insertions(+), 38 deletions(-) diff --git a/drivers/gpu/drm/drm_scdc_helper.c b/drivers/gpu/drm/drm_scdc_helper.c index 3cd96a95736d..7d1b0f011d33 100644 --- a/drivers/gpu/drm/drm_scdc_helper.c +++ b/drivers/gpu/drm/drm_scdc_helper.c @@ -194,19 +194,26 @@ EXPORT_SYMBOL(drm_scdc_set_scrambling); * @adapter: I2C adapter for DDC channel * @set: ret or reset the high clock ratio * - * TMDS clock ratio calculations go like this: - * TMDS character = 10 bit TMDS encoded value - * TMDS character rate = The rate at which TMDS characters are transmitted(Mcsc) - * TMDS bit rate = 10x TMDS character rate - * As per the spec: - * TMDS clock rate for pixel clock < 340 MHz = 1x the character rate - * = 1/10 pixel clock rate - * TMDS clock rate for pixel clock > 340 MHz = 0.25x the character rate - * = 1/40 pixel clock rate - * - * Writes to the TMDS config register over SCDC channel, and: - * sets TMDS clock ratio to 1/40 when set = 1 - * sets TMDS clock ratio to 1/10 when set = 0 + * + * TMDS clock ratio calculations go like this: + * TMDS character = 10 bit TMDS encoded value + * + * TMDS character rate = The rate at which TMDS characters are + * transmitted (Mcsc) + * + * TMDS bit rate = 10x TMDS character rate + * + * As per the spec: + * TMDS clock rate for pixel clock < 340 MHz = 1x the character + * rate = 1/10 pixel clock rate + * + * TMDS clock rate for pixel clock > 340 MHz = 0.25x the character + * rate = 1/40 pixel clock rate + * + * Writes to the TMDS config register over SCDC channel, and: + * sets TMDS clock ratio to 1/40 when set = 1 + * + * sets TMDS clock ratio to 1/10 when set = 0 * * Returns: * True if write is successful, false otherwise. diff --git a/include/drm/drm_scdc_helper.h b/include/drm/drm_scdc_helper.h index c25122bb490a..f92eb2094d6b 100644 --- a/include/drm/drm_scdc_helper.h +++ b/include/drm/drm_scdc_helper.h @@ -131,31 +131,6 @@ static inline int drm_scdc_writeb(struct i2c_adapter *adapter, u8 offset, bool drm_scdc_get_scrambling_status(struct i2c_adapter *adapter); -/** - * drm_scdc_set_scrambling - enable scrambling - * @adapter: I2C adapter for DDC channel - * @enable: bool to indicate if scrambling is to be enabled/disabled - * - * Writes the TMDS config register over SCDC channel, and: - * enables scrambling when enable = 1 - * disables scrambling when enable = 0 - * - * Returns: - * True if scrambling is set/reset successfully, false otherwise. - */ bool drm_scdc_set_scrambling(struct i2c_adapter *adapter, bool enable); - -/** - * drm_scdc_set_high_tmds_clock_ratio - set TMDS clock ratio - * @adapter: I2C adapter for DDC channel - * @set: ret or reset the high clock ratio - * - * Writes to the TMDS config register over SCDC channel, and: - * sets TMDS clock ratio to 1/40 when set = 1 - * sets TMDS clock ratio to 1/10 when set = 0 - * - * Returns: - * True if write is successful, false otherwise. - */ bool drm_scdc_set_high_tmds_clock_ratio(struct i2c_adapter *adapter, bool set); #endif -- 2.20.1