From 6b54783620bcfaff37ad41e957d29c326211cc18 Mon Sep 17 00:00:00 2001 From: Heikki Krogerus Date: Mon, 2 Feb 2015 15:37:04 +0200 Subject: [PATCH] clk: fractional-divider: support for divider bypassing If the divider or multiplier values are 0 in the register, bypassing the divider and returning the parent clock rate in clk_fd_recalc_rate(). Signed-off-by: Heikki Krogerus Reviewed-by: Stephen Boyd Signed-off-by: Michael Turquette [mturquette@linaro.org: fixed commitlog typo] --- drivers/clk/clk-fractional-divider.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/clk/clk-fractional-divider.c b/drivers/clk/clk-fractional-divider.c index 82a59d0086cc..6aa72d9d79ba 100644 --- a/drivers/clk/clk-fractional-divider.c +++ b/drivers/clk/clk-fractional-divider.c @@ -36,6 +36,9 @@ static unsigned long clk_fd_recalc_rate(struct clk_hw *hw, m = (val & fd->mmask) >> fd->mshift; n = (val & fd->nmask) >> fd->nshift; + if (!n || !m) + return parent_rate; + ret = (u64)parent_rate * m; do_div(ret, n); -- 2.20.1