From 619d4f7e219f4e65137b66ac878cd1eba8e51e10 Mon Sep 17 00:00:00 2001 From: Emil Velikov Date: Mon, 11 Apr 2011 20:43:23 +0100 Subject: [PATCH] drm/nv50: improve nv50_pm_get_clock() Many of the nv50 cards have their shader and/or memory pll disabled at some stage. This patch addresses those cases, so that the function returns the correct frequency. When the shader pll is disabled, the blob reports 2*core clock Whereas for memory, the data stored in the vbios. This action is incorrect as some vbioses store a clock value that is less than the refference clock of the pll. Thus we are reporting the reff_clk as it is the frequency the pll actually operates v2 - Convert NV_INFO() messages to NV_DEBUG() Provide more information in the actuall message Signed-off-by: Emil Velikov Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/nv50_pm.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/drivers/gpu/drm/nouveau/nv50_pm.c b/drivers/gpu/drm/nouveau/nv50_pm.c index 7dbb305d7e63..8a2810011bda 100644 --- a/drivers/gpu/drm/nouveau/nv50_pm.c +++ b/drivers/gpu/drm/nouveau/nv50_pm.c @@ -47,6 +47,21 @@ nv50_pm_clock_get(struct drm_device *dev, u32 id) reg0 = nv_rd32(dev, pll.reg + 0); reg1 = nv_rd32(dev, pll.reg + 4); + + if ((reg0 & 0x80000000) == 0) { + if (id == PLL_SHADER) { + NV_DEBUG(dev, "Shader PLL is disabled. " + "Shader clock is twice the core\n"); + ret = nv50_pm_clock_get(dev, PLL_CORE); + if (ret > 0) + return ret << 1; + } else if (id == PLL_MEMORY) { + NV_DEBUG(dev, "Memory PLL is disabled. " + "Memory clock is equal to the ref_clk\n"); + return pll.refclk; + } + } + P = (reg0 & 0x00070000) >> 16; N = (reg1 & 0x0000ff00) >> 8; M = (reg1 & 0x000000ff); -- 2.20.1