From 598056d5af8fef1dbe8f96f5c2b641a528184e5a Mon Sep 17 00:00:00 2001 From: Nick Piggin Date: Thu, 22 May 2008 00:10:56 +1000 Subject: [PATCH] [POWERPC] Fix rmb to order cacheable vs. noncacheable lwsync is explicitly defined not to have any effect on the ordering of accesses to device memory, so it cannot be used for rmb(). sync appears to be the only barrier which fits the bill. Signed-off-by: Nick Piggin Acked-by: Benjamin Herrenschmidt Signed-off-by: Paul Mackerras --- include/asm-powerpc/system.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/asm-powerpc/system.h b/include/asm-powerpc/system.h index 2b6559a6d113..5235f875b932 100644 --- a/include/asm-powerpc/system.h +++ b/include/asm-powerpc/system.h @@ -34,7 +34,7 @@ * SMP since it is only used to order updates to system memory. */ #define mb() __asm__ __volatile__ ("sync" : : : "memory") -#define rmb() __asm__ __volatile__ (__stringify(LWSYNC) : : : "memory") +#define rmb() __asm__ __volatile__ ("sync" : : : "memory") #define wmb() __asm__ __volatile__ ("sync" : : : "memory") #define read_barrier_depends() do { } while(0) -- 2.20.1