From 567649086a73381cf332989ae16bc808618d7ef2 Mon Sep 17 00:00:00 2001
From: Zongdong Jiao <zongdong.jiao@amlogic.com>
Date: Wed, 9 Oct 2019 20:54:05 +0800
Subject: [PATCH] hdmitx: update PHY parameters [2/2]

PD#SWPL-14962

Problem:
need update PHY parameters on condition

Solution:
update PHY parameters on condition

Verify:
SM1/S905D3

Change-Id: I29cae7298140ab7a41a55b8891d4acd74fec8f5e
Signed-off-by: Zongdong Jiao <zongdong.jiao@amlogic.com>
---
 .../vout/hdmitx/hdmi_tx_20/hw/hdmi_tx_hw.c    | 39 +++++++++++++++++++
 1 file changed, 39 insertions(+)

diff --git a/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hdmi_tx_hw.c b/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hdmi_tx_hw.c
index 6f746c356bc3..5c88c9e93f4e 100644
--- a/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hdmi_tx_hw.c
+++ b/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hdmi_tx_hw.c
@@ -48,6 +48,7 @@
 #include <linux/arm-smccc.h>
 #include "checksha.h"
 #include <linux/amlogic/media/sound/hdmi_earc.h>
+#include <linux/amlogic/scpi_protocol.h>
 
 static void mode420_half_horizontal_para(void);
 static void hdmi_phy_suspend(void);
@@ -1847,6 +1848,40 @@ static void hdmitx_set_pll(struct hdmitx_dev *hdev)
 	hdmitx_set_clk(hdev);
 }
 
+static void set_phy_6g_sm1(void)
+{
+	unsigned char info[12] = {0};
+	int idx = 1;
+
+	memset(info, 0, sizeof(info));
+	if (scpi_get_ring_value(info) != 0)
+		memset(info, 0, sizeof(info));
+	pr_info("value: %d\n", info[3]);
+	if (info[3] == 0)
+		idx = 1;
+	else if (info[3] <= 127)
+		idx = 0;
+	else if (info[3] <= 138)
+		idx = 1;
+	else
+		idx = 2;
+
+	switch (idx) {
+	case 0:
+		hd_write_reg(P_HHI_HDMI_PHY_CNTL0, 0x07EB65F3);
+		break;
+	case 1:
+		hd_write_reg(P_HHI_HDMI_PHY_CNTL0, 0x37EB65C4);
+		break;
+	case 2:
+		hd_write_reg(P_HHI_HDMI_PHY_CNTL0, 0x37EB65A4);
+		break;
+	default:
+		hd_write_reg(P_HHI_HDMI_PHY_CNTL0, 0x37EB65C4);
+		break;
+	}
+}
+
 static void set_phy_by_mode(unsigned int mode)
 {
 	struct hdmitx_dev *hdev = get_hdmitx_device();
@@ -1895,6 +1930,10 @@ static void set_phy_by_mode(unsigned int mode)
 	case MESON_CPU_ID_SM1:
 		switch (mode) {
 		case HDMI_PHYPARA_6G: /* 5.94/4.5/3.7Gbps */
+			set_phy_6g_sm1();
+			hd_write_reg(P_HHI_HDMI_PHY_CNTL3, 0x2ab0ff3b);
+			hd_write_reg(P_HHI_HDMI_PHY_CNTL5, 0x0000080b);
+			break;
 		case HDMI_PHYPARA_4p5G:
 		case HDMI_PHYPARA_3p7G:
 			hd_write_reg(P_HHI_HDMI_PHY_CNTL0, 0x37eb65c4);
-- 
2.20.1