From 566f74f6b2f8b85d5b8d6caaf97e5672cecd3e3e Mon Sep 17 00:00:00 2001 From: David Daney Date: Thu, 23 Oct 2008 17:56:35 -0700 Subject: [PATCH] MIPS: Consider value of c0_ebase when computing value of exception base. It just so happens to be zero on all currently supported systems so this hasn't bitten yet ... [Ralf: Original patch from Cavium; handling of set_uncached_handler() and de-ifdef'ed trap_init() implementation by me.] Signed-off-by: Tomaso Paoletti Signed-off-by: David Daney Signed-off-by: Ralf Baechle --- arch/mips/kernel/traps.c | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index 80b9e070c20..3f6de76d485 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c @@ -1555,6 +1555,8 @@ void __cpuinit set_uncached_handler(unsigned long offset, void *addr, #ifdef CONFIG_64BIT unsigned long uncached_ebase = TO_UNCAC(ebase); #endif + if (cpu_has_mips_r2) + ebase += (read_c0_ebase() & 0x3ffff000); if (!addr) panic(panic_null_cerr); @@ -1588,8 +1590,11 @@ void __init trap_init(void) if (cpu_has_veic || cpu_has_vint) ebase = (unsigned long) alloc_bootmem_low_pages(0x200 + VECTORSPACING*64); - else + else { ebase = CAC_BASE; + if (cpu_has_mips_r2) + ebase += (read_c0_ebase() & 0x3ffff000); + } per_cpu_trap_init(); @@ -1697,11 +1702,11 @@ void __init trap_init(void) if (cpu_has_vce) /* Special exception: R4[04]00 uses also the divec space. */ - memcpy((void *)(CAC_BASE + 0x180), &except_vec3_r4000, 0x100); + memcpy((void *)(ebase + 0x180), &except_vec3_r4000, 0x100); else if (cpu_has_4kex) - memcpy((void *)(CAC_BASE + 0x180), &except_vec3_generic, 0x80); + memcpy((void *)(ebase + 0x180), &except_vec3_generic, 0x80); else - memcpy((void *)(CAC_BASE + 0x080), &except_vec3_generic, 0x80); + memcpy((void *)(ebase + 0x080), &except_vec3_generic, 0x80); signal_init(); #ifdef CONFIG_MIPS32_COMPAT -- 2.20.1