From 54ad33daf4b1d91c06152b93a5adc21aea03503d Mon Sep 17 00:00:00 2001 From: hwangjae lee Date: Tue, 15 May 2018 16:45:21 +0900 Subject: [PATCH] [9610] fbdev: dpu: DPP configure is modified to Exynos9610 spec 1. IDMA Number, SFR address, SFR setting value is changed. 2. Base address setting function is changed. 3. DECON sram share size is changed. Change-Id: I430a908233b880c4d9b057cdd34de51b541db8d8 Signed-off-by: hwangjae lee --- .../fbdev/exynos/dpu20/cal_9610/decon_cal.h | 26 ++-- .../fbdev/exynos/dpu20/cal_9610/decon_reg.c | 42 +++--- .../fbdev/exynos/dpu20/cal_9610/dpp_cal.h | 4 +- .../fbdev/exynos/dpu20/cal_9610/dpp_reg.c | 123 +++++++++++------- .../fbdev/exynos/dpu20/cal_9610/regs-decon.h | 7 +- .../fbdev/exynos/dpu20/cal_9610/regs-dpp.h | 54 ++------ 6 files changed, 116 insertions(+), 140 deletions(-) diff --git a/drivers/video/fbdev/exynos/dpu20/cal_9610/decon_cal.h b/drivers/video/fbdev/exynos/dpu20/cal_9610/decon_cal.h index 630e445ea1ce..89f31484b0c4 100644 --- a/drivers/video/fbdev/exynos/dpu20/cal_9610/decon_cal.h +++ b/drivers/video/fbdev/exynos/dpu20/cal_9610/decon_cal.h @@ -2,7 +2,7 @@ * Copyright (c) 2018 Samsung Electronics Co., Ltd. * http://www.samsung.com * - * Header file for Exynos9820 DECON CAL + * Header file for Exynos9610 DECON CAL * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -16,29 +16,20 @@ #define CEIL(x) ((x-(u32)(x) > 0 ? (u32)(x+1) : (u32)(x))) -#define CHIP_VER (9820) +#define CHIP_VER (9610) #define MAX_DECON_CNT 3 -#define MAX_DECON_WIN 6 -#define MAX_DPP_SUBDEV 7 +#define MAX_DECON_WIN 4 +#define MAX_DPP_SUBDEV 5 enum decon_idma_type { - IDMA_G0 = 0, - IDMA_G1, + IDMA_GF = 0, /* GF in case of Exynos9610 */ IDMA_VG0, - IDMA_VG1, - IDMA_VGF0, - IDMA_VGF1, /* VGRF in case of Exynos9810 */ + IDMA_G0, + IDMA_G1, ODMA_WB, MAX_DECON_DMA_TYPE, }; -#define IDMA_GF0 IDMA_G0 -#define IDMA_GF1 IDMA_G1 -#define IDMA_VG IDMA_VG0 -#define IDMA_VGF IDMA_VG1 -#define IDMA_VGS IDMA_VGF0 -#define IDMA_VGRFS IDMA_VGF1 - enum decon_fifo_mode { DECON_FIFO_00K = 0, DECON_FIFO_04K, @@ -94,8 +85,7 @@ enum decon_data_path { enum decon_scaler_path { SCALERPATH_OFF = 0x0, - SCALERPATH_VGF = 0x1, - SCALERPATH_VGRF = 0x2, + SCALERPATH_VG0 = 0x1, }; enum decon_path_cfg { diff --git a/drivers/video/fbdev/exynos/dpu20/cal_9610/decon_reg.c b/drivers/video/fbdev/exynos/dpu20/cal_9610/decon_reg.c index 308eaa64e347..ff9478c0d5c8 100644 --- a/drivers/video/fbdev/exynos/dpu20/cal_9610/decon_reg.c +++ b/drivers/video/fbdev/exynos/dpu20/cal_9610/decon_reg.c @@ -1,7 +1,7 @@ /* - * linux/drivers/video/fbdev/exynos/dpu_9810/decon_reg.c + * linux/drivers/video/fbdev/exynos/dpu20/cal_9610/decon_reg.c * - * Copyright 2013-2017 Samsung Electronics + * Copyright 2018 Samsung Electronics * SeungBeom Park * * This program is free software; you can redistribute it and/or modify @@ -1434,7 +1434,7 @@ static void decon_reg_init_probe(u32 id, u32 dsi_idx, struct decon_param *p) decon_reg_set_clkgate_mode(id, 0); - decon_reg_set_sram_share(id, DECON_FIFO_04K); + decon_reg_set_sram_share(id, DECON_FIFO_08K); decon_reg_set_operation_mode(id, psr->psr_mode); @@ -1751,7 +1751,7 @@ int decon_reg_init(u32 id, u32 dsi_idx, struct decon_param *p) decon_reg_set_te_qactive_pll_mode(id, 1); if (id == 0) - decon_reg_set_sram_share(id, DECON_FIFO_04K); + decon_reg_set_sram_share(id, DECON_FIFO_08K); else if (id == 2) decon_reg_set_sram_share(id, DECON_FIFO_12K); @@ -2125,22 +2125,16 @@ u32 DPU_DMA2CH(u32 dma) u32 ch_id; switch (dma) { - case IDMA_GF0: - ch_id = 0; - break; - case IDMA_GF1: + case IDMA_G0: ch_id = 2; break; - case IDMA_VG: - ch_id = 4; - break; - case IDMA_VGF: + case IDMA_G1: ch_id = 3; break; - case IDMA_VGS: - ch_id = 5; + case IDMA_GF: + ch_id = 0; break; - case IDMA_VGRFS: + case IDMA_VG0: ch_id = 1; break; default: @@ -2156,23 +2150,17 @@ u32 DPU_CH2DMA(u32 ch) u32 dma; switch (ch) { - case 0: - dma = IDMA_GF0; - break; - case 1: - dma = IDMA_VGRFS; - break; case 2: - dma = IDMA_GF1; + dma = IDMA_G0; break; case 3: - dma = IDMA_VGF; + dma = IDMA_G1; break; - case 4: - dma = IDMA_VG; + case 0: + dma = IDMA_GF; break; - case 5: - dma = IDMA_VGS; + case 1: + dma = IDMA_VG0; break; default: decon_warn("channal(%d) is invalid\n", ch); diff --git a/drivers/video/fbdev/exynos/dpu20/cal_9610/dpp_cal.h b/drivers/video/fbdev/exynos/dpu20/cal_9610/dpp_cal.h index c9a04885185f..a389fad56596 100644 --- a/drivers/video/fbdev/exynos/dpu20/cal_9610/dpp_cal.h +++ b/drivers/video/fbdev/exynos/dpu20/cal_9610/dpp_cal.h @@ -2,7 +2,7 @@ * Copyright (c) 2018 Samsung Electronics Co., Ltd. * http://www.samsung.com * - * Header file for Exynos9820 DPP CAL + * Header file for Exynos9610 DPP CAL * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -14,7 +14,7 @@ #include "../decon.h" -#define MAX_DPP_CNT 6 +#define MAX_DPP_CNT 4 #define SRC_SIZE_MULTIPLE 1 #define SRC_WIDTH_MIN 16 diff --git a/drivers/video/fbdev/exynos/dpu20/cal_9610/dpp_reg.c b/drivers/video/fbdev/exynos/dpu20/cal_9610/dpp_reg.c index c304b7d05f44..9fd7dbae1382 100644 --- a/drivers/video/fbdev/exynos/dpu20/cal_9610/dpp_reg.c +++ b/drivers/video/fbdev/exynos/dpu20/cal_9610/dpp_reg.c @@ -1,6 +1,6 @@ -/* linux/drivers/video/exynos/fbdev/dpu_9810/dpp_regs.c +/* linux/drivers/video/exynos/fbdev/dpu20/cal_9610/dpp_regs.c * - * Copyright (c) 2017 Samsung Electronics Co., Ltd. + * Copyright (c) 2018 Samsung Electronics Co., Ltd. * http://www.samsung.com * * Samsung EXYNOS9 SoC series Display Pre Processor driver @@ -660,26 +660,86 @@ static void wb_mux_reg_set_uv_offset(u32 id, u32 off_x, u32 off_y) WB_UV_OFFSET_Y_MASK | WB_UV_OFFSET_X_MASK); } +void dma_reg_set_in_base_addr(u32 id, u32 addr_y, u32 addr_c) +{ + dma_write(id, IDMA_IN_BASE_ADDR_Y, addr_y); + dma_write(id, IDMA_IN_BASE_ADDR_C, addr_c); +} + +void dma_reg_set_in_2b_base_addr(u32 id, u32 addr_y, u32 addr_c) +{ + dma_write(id, IDMA_IN_BASE_ADDR_Y2, addr_y); + dma_write(id, IDMA_IN_BASE_ADDR_C2, addr_c); +} + +void dpp_reg_set_buf_1p_addr(u32 id, struct dpp_params_info *p) +{ + /* For AFBC stream, BASE_ADDR_C must be same with BASE_ADDR_Y */ + dma_reg_set_in_base_addr(id, p->addr[0], p->addr[0]); +} + +void dpp_reg_set_buf_2p_addr(u32 id, struct dpp_params_info *p) +{ + dma_reg_set_in_base_addr(id, p->addr[0], p->addr[1]); +} + +void dpp_reg_set_buf_4p_addr(u32 id, struct dpp_params_info *p) +{ + dma_reg_set_in_base_addr(id, p->addr[0], p->addr[1]); + dma_reg_set_in_2b_base_addr(id, p->addr[2], p->addr[3]); +} + +void dma_reg_set_luma_2bit_stride(u32 id, u32 stride) +{ + u32 val, mask; + + val = IDMA_LUMA_2B_STRIDE(stride); + mask = IDMA_LUMA_2B_STRIDE_MASK; + dma_write_mask(id, IDMA_2BIT_STRIDE, val, mask); +} + +void dma_reg_set_chroma_2bit_stride(u32 id, u32 stride) +{ + u32 val, mask; + + val = IDMA_CHROMA_2B_STRIDE(stride); + mask = IDMA_CHROMA_2B_STRIDE_MASK; + dma_write_mask(id, IDMA_2BIT_STRIDE, val, mask); +} + +void dpp_reg_set_buf_addr(u32 id, struct dpp_params_info *p) +{ + if (p->is_4p) { + dpp_reg_set_buf_4p_addr(id, p); + dma_reg_set_luma_2bit_stride(id, p->y_2b_strd); + dma_reg_set_chroma_2bit_stride(id, p->c_2b_strd); + } else { + if (p->is_comp) { + dpp_reg_set_buf_1p_addr(id, p); + } else { + dpp_reg_set_buf_2p_addr(id, p); + } + } + dpp_dbg("dpp id : %d, 1st-plane : 0x%p, 2nd-plane : 0x%p ", + id, (void *)p->addr[0], (void *)p->addr[1]); + dpp_dbg("3rd-plane : 0x%p, 4th-plane : 0x%p\n", + (void *)p->addr[2], (void *)p->addr[3]); + +} + /********** IDMA and ODMA combination CAL functions **********/ +#if 0 static void dma_reg_set_base_addr(u32 id, struct dpp_params_info *p, const unsigned long attr) { + dpp_info("%s, %d dpp[%d] attr[%lu]\n", __func__, __LINE__, id, attr); if (test_bit(DPP_ATTR_IDMA, &attr)) { + dpp_info("%s, %d dpp[%d] attr[%lu]\n", __func__, __LINE__, id, attr); dma_write(id, IDMA_IN_BASE_ADDR_Y, p->addr[0]); if (p->is_comp) - dma_write(id, IDMA_IN_BASE_ADDR_C, p->addr[0]); + dma_write(id, IDMA_IN_BASE_ADDR_Y, p->addr[0]); else - dma_write(id, IDMA_IN_BASE_ADDR_C, p->addr[1]); - if (p->is_4p) { - dma_write(id, IDMA_IN_BASE_ADDR_Y2, p->addr[2]); - dma_write(id, IDMA_IN_BASE_ADDR_C2, p->addr[3]); - dma_write_mask(id, IDMA_2BIT_STRIDE, - IDMA_LUMA_2B_STRIDE(p->y_2b_strd), - IDMA_LUMA_2B_STRIDE_MASK); - dma_write_mask(id, IDMA_2BIT_STRIDE, - IDMA_CHROMA_2B_STRIDE(p->c_2b_strd), - IDMA_CHROMA_2B_STRIDE_MASK); - } + dma_write(id, IDMA_IN_BASE_ADDR_Y, p->addr[1]); } else if (test_bit(DPP_ATTR_ODMA, &attr)) { dma_write(id, ODMA_IN_BASE_ADDR_Y, p->addr[0]); dma_write(id, ODMA_IN_BASE_ADDR_C, p->addr[1]); @@ -688,7 +748,7 @@ static void dma_reg_set_base_addr(u32 id, struct dpp_params_info *p, (void *)p->addr[0], (void *)p->addr[1], (void *)p->addr[2], (void *)p->addr[3]); } - +#endif /********** IDMA, ODMA, DPP and WB MUX combination CAL functions **********/ static void dma_dpp_reg_set_coordinates(u32 id, struct dpp_params_info *p, const unsigned long attr) @@ -824,36 +884,6 @@ static int dma_dpp_reg_set_format(u32 id, struct dpp_params_info *p, fmt_type = DPP_IMG_FORMAT_YUV420_8P2; is_yuv = 1; break; - case DECON_PIXEL_FORMAT_NV16: - fmt = IDMA_IMG_FORMAT_YVU422_2P; - fmt_type = DPP_IMG_FORMAT_YUV422_8P; - is_yuv = 1; - break; - case DECON_PIXEL_FORMAT_NV61: - fmt = IDMA_IMG_FORMAT_YUV422_2P; - fmt_type = DPP_IMG_FORMAT_YUV422_8P; - is_yuv = 1; - break; - case DECON_PIXEL_FORMAT_NV16M_P210: - fmt = IDMA_IMG_FORMAT_YUV422_P210; - fmt_type = DPP_IMG_FORMAT_YUV422_P210; - is_yuv = 1; - break; - case DECON_PIXEL_FORMAT_NV61M_P210: - fmt = IDMA_IMG_FORMAT_YVU422_P210; - fmt_type = DPP_IMG_FORMAT_YUV422_P210; - is_yuv = 1; - break; - case DECON_PIXEL_FORMAT_NV16M_S10B: - fmt = IDMA_IMG_FORMAT_YUV422_8P2; - fmt_type = DPP_IMG_FORMAT_YUV422_8P2; - is_yuv = 1; - break; - case DECON_PIXEL_FORMAT_NV61M_S10B: - fmt = IDMA_IMG_FORMAT_YVU422_8P2; - fmt_type = DPP_IMG_FORMAT_YUV422_8P2; - is_yuv = 1; - break; default: dpp_err("Unsupported Format\n"); return -EINVAL; @@ -1043,7 +1073,8 @@ void dpp_reg_configure_params(u32 id, struct dpp_params_info *p, idma_reg_set_rotation(id, p->rot); /* configure base address of IDMA and ODMA */ - dma_reg_set_base_addr(id, p, attr); + dpp_reg_set_buf_addr(id, p); +// dma_reg_set_base_addr(id, p, attr); if (test_bit(DPP_ATTR_BLOCK, &attr)) idma_reg_set_block_mode(id, p->is_block, p->block.x, p->block.y, diff --git a/drivers/video/fbdev/exynos/dpu20/cal_9610/regs-decon.h b/drivers/video/fbdev/exynos/dpu20/cal_9610/regs-decon.h index 50a6e9fc4421..503928ef5049 100644 --- a/drivers/video/fbdev/exynos/dpu20/cal_9610/regs-decon.h +++ b/drivers/video/fbdev/exynos/dpu20/cal_9610/regs-decon.h @@ -1,9 +1,9 @@ /* - * linux/drivers/video/fbdev/exynos/dpu_9810/regs_decon.h + * linux/drivers/video/fbdev/exynos/dpu20/cal_9610/regs_decon.h * * Register definition file for Samsung DECON driver * - * Copyright (c) 2014 Samsung Electronics + * Copyright (c) 2018 Samsung Electronics * SeungBeom park * * This program is free software; you can redistribute it and/or modify @@ -129,8 +129,6 @@ #define TIME_OUT_VALUE 0x0048 #define INTERRUPT_PENDING 0x004C -#define DPU_DQE_DIMMING_END_INT_PEND (1 << 21) -#define DPU_DQE_DIMMING_START_INT_PEND (1 << 20) #define DPU_FRAME_DONE_INT_PEND (1 << 13) #define DPU_FRAME_START_INT_PEND (1 << 12) #define DPU_EXTRA_INT_PEND (1 << 4) @@ -141,7 +139,6 @@ #define SHADOW_REG_UPDATE_REQ 0x0060 #define SHADOW_REG_UPDATE_REQ_GLOBAL (1 << 31) -#define SHADOW_REG_UPDATE_REQ_DQE (1 << 28) #define SHADOW_REG_UPDATE_REQ_WIN(_win) (1 << (_win)) #define SHADOW_REG_UPDATE_REQ_FOR_DECON (0x3f) diff --git a/drivers/video/fbdev/exynos/dpu20/cal_9610/regs-dpp.h b/drivers/video/fbdev/exynos/dpu20/cal_9610/regs-dpp.h index 8e5881c9d8de..97041ee47a39 100644 --- a/drivers/video/fbdev/exynos/dpu20/cal_9610/regs-dpp.h +++ b/drivers/video/fbdev/exynos/dpu20/cal_9610/regs-dpp.h @@ -1,4 +1,4 @@ -/* linux/drivers/video/fbdev/dpu20/cal_9820/regs-dpp.h +/* linux/drivers/video/fbdev/dpu20/cal_9610/regs-dpp.h * * Copyright (c) 2018 Samsung Electronics Co., Ltd. * http://www.samsung.com @@ -14,15 +14,8 @@ #define DPP_REGS_H_ /* - * DPU_DMA SFR base address : 0x19070000 - * - GLOBAL : 0x19070000 - * - IDMA GF0 : 0x19071000 - * - IDMA GF1 : 0x19072000 - * - IDMA VG : 0x19073000 - * - IDMA VGS : 0x19074000 - * - IDMA VGF : 0x19075000 - * - IDMA VGRFS : 0x19076000 - * - ODMA : 0x19077000 + * 1 - DMA.base + * : 0x1488_0000 */ #define DPU_DMA_VERSION 0x0000 @@ -40,7 +33,7 @@ #define DMA_SFR_CGEN(_v) ((_v) << 31) #define DMA_SFR_CGEN_MASK (1 << 31) #define DMA_INT_CGEN(_v) ((_v) << 0) -/* [9820] bit range is changed [28:0] -> [30:0] */ +/* [9610] bit range is changed [28:0] -> [30:0] */ #define DMA_INT_CGEN_MASK (0x7FFFFFFF << 0) #define DPU_DMA_TEST_PATTERN0_3 0x0020 @@ -52,7 +45,7 @@ #define DPU_DMA_TEST_PATTERN1_1 0x0038 #define DPU_DMA_TEST_PATTERN1_0 0x003C -/* [9820] add AFBC QoS value */ +/* [9610] add AFBC QoS value */ #define DPU_DMA_AFBC_QOS 0x0060 #define FBC_L5_PAYLOAD_QOS(_v) ((_v) << 28) #define FBC_L5_PAYLOAD_QOS_MASK (0xF << 28) @@ -117,9 +110,6 @@ #define INSTANT_OFF_NOT_PENDING (0) #define IDMA_IRQ 0x0004 -/* [9820] AFBC_CONFLICT_IRQ is added */ -#define IDMA_AFBC_CONFLICT_IRQ (1 << 25) -/* [9820] MO_CONFLICT_IRQ -> VR_CONFLICT_IRQ */ #define IDMA_VR_CONFLICT_IRQ (1 << 24) #define IDMA_AFBC_TIMEOUT_IRQ (1 << 23) #define IDMA_RECOVERY_START_IRQ (1 << 22) @@ -128,10 +118,7 @@ #define IDMA_READ_SLAVE_ERROR (1 << 19) #define IDMA_STATUS_DEADLOCK_IRQ (1 << 17) #define IDMA_STATUS_FRAMEDONE_IRQ (1 << 16) -#define IDMA_ALL_IRQ_CLEAR (0x3FB << 16) -/* [9820] AFBC_CONFLICT_IRQ_MASK is added */ -#define IDMA_AFBC_CONFLICT_MASK (1 << 10) -/* [9820] MO_CONFLICT_IRQ_MASK -> VR_CONFLICT_IRQ_MASK */ +#define IDMA_ALL_IRQ_CLEAR (0x1FB << 16) #define IDMA_VR_CONFLICT_MASK (1 << 9) #define IDMA_AFBC_TIMEOUT_MASK (1 << 8) #define IDMA_RECOVERY_START_MASK (1 << 7) @@ -140,7 +127,7 @@ #define IDMA_READ_SLAVE_ERROR_MASK (1 << 4) #define IDMA_IRQ_DEADLOCK_MASK (1 << 2) #define IDMA_IRQ_FRAMEDONE_MASK (1 << 1) -#define IDMA_ALL_IRQ_MASK (0x3FB << 1) +#define IDMA_ALL_IRQ_MASK (0x1FB << 1) #define IDMA_IRQ_ENABLE (1 << 0) #define IDMA_IN_CON 0x0008 @@ -171,13 +158,7 @@ #define IDMA_IMG_FORMAT_YVU420_8P2 (27) #define IDMA_IMG_FORMAT_YUV420_P010 (29) #define IDMA_IMG_FORMAT_YVU420_P010 (28) -/* [9820] Below IDMA formats are added */ -#define IDMA_IMG_FORMAT_YVU422_2P (56) -#define IDMA_IMG_FORMAT_YUV422_2P (57) -#define IDMA_IMG_FORMAT_YVU422_8P2 (58) -#define IDMA_IMG_FORMAT_YUV422_8P2 (59) -#define IDMA_IMG_FORMAT_YVU422_P210 (60) -#define IDMA_IMG_FORMAT_YUV422_P210 (61) + #define IDMA_ROTATION(_v) ((_v) << 8) #define IDMA_ROTATION_MASK (7 << 8) #define IDMA_ROTATION_X_FLIP (1 << 8) @@ -288,7 +269,7 @@ */ #define ODMA_ENABLE 0x0000 #define ODMA_SRSET (1 << 24) -/* [9820] removed ? */ +/* [9610] removed ? */ //#define ODMA_SFR_CLOCK_GATE_EN (1 << 10) //#define ODMA_SRAM_CLOCK_GATE_EN (1 << 9) //#define ODMA_ALL_CLOCK_GATE_EN_MASK (0x3 << 9) @@ -391,7 +372,7 @@ #define ODMA_DYNAMIC_GATING_EN 0x0354 #define ODMA_DG_EN(_n, _v) ((_v) << (_n)) #define ODMA_DG_EN_MASK(_n) (1 << (_n)) -#define ODMA_DG_EN_ALL (0x7FF << 0) /* 9820 */ +#define ODMA_DG_EN_ALL (0x7FF << 0) /* 9610 */ #define ODMA_CHAN_CONTROL 0x0360 #define ODMA_CHAN_DATA 0x0364 @@ -448,7 +429,7 @@ #define DPU_WB_DYNAMIC_GATING_EN 0x0A54 #define WB_DG_EN(_n, _v) ((_v) << (_n)) #define WB_DG_EN_MASK(_n) (1 << (_n)) -#define WB_DG_EN_ALL (0xF << 0) /* 9820 */ +#define WB_DG_EN_ALL (0xF << 0) /* 9610 */ #define DPU_WB_CFG_ERR_STATE 0x0D08 #define WB_CFG_ERR_GET(_v) (((_v) >> 0) & 0xF) @@ -458,17 +439,10 @@ #define WB_CFG_ERR_MIN_SIZE (1 << 0) /* - * DPP SFR base address : 0x19020000 - * - DPP GF0 : 0x19021000 - * - DPP GF1 : 0x19022000 - * - DPP VG : 0x19023000 - * - DPP VGF : 0x19024000 - * - DPP VGS : 0x19025000 - * - DPP VGRFS : 0x19026000 + * DPP SFR base address : 0x14890000 */ #define DPP_ENABLE 0x0000 #define DPP_SRSET (1 << 24) -#define DPP_HDR_SEL (1 << 11) #define DPP_SFR_CLOCK_GATE_EN (1 << 10) #define DPP_SRAM_CLOCK_GATE_EN (1 << 9) #define DPP_INT_CLOCK_GATE_EN (1 << 8) @@ -506,10 +480,6 @@ #define DPP_IMG_FORMAT_YUV420_8P (2 << 0) #define DPP_IMG_FORMAT_YUV420_P010 (3 << 0) #define DPP_IMG_FORMAT_YUV420_8P2 (4 << 0) -/* [9820] 3 kinds of YUV422 formats are added to DPP format */ -#define DPP_IMG_FORMAT_YUV422_8P (5 << 0) -#define DPP_IMG_FORMAT_YUV422_P210 (6 << 0) -#define DPP_IMG_FORMAT_YUV422_8P2 (7 << 0) #define DPP_IMG_SIZE 0x0018 #define DPP_IMG_HEIGHT(_v) ((_v) << 16) #define DPP_IMG_HEIGHT_MASK (0x1FFF << 16) -- 2.20.1