From 4c6c32b3f856346158161a8c9824b4dd2bff0893 Mon Sep 17 00:00:00 2001 From: =?utf8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Mon, 29 Nov 2010 08:58:14 +0100 Subject: [PATCH] ARM: mx25: fix offset for usb host controller MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit In commit 2c20b9f (ARM: mx25: dynamically allocate mxc-ehci devices) I changed the offset to the value specified in the reference manual intending to test this change on hardware. This slipped through and now prooved to be wrong. So fix it and add a comment about the documentation being wrong. Reported-by: Jaume Ribot Cc: Michael Trimarchi Cc: Shawn Guo Signed-off-by: Uwe Kleine-König Signed-off-by: Sascha Hauer --- arch/arm/plat-mxc/include/mach/mx25.h | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/arch/arm/plat-mxc/include/mach/mx25.h b/arch/arm/plat-mxc/include/mach/mx25.h index 024bebe4da11..087cd7ac8d52 100644 --- a/arch/arm/plat-mxc/include/mach/mx25.h +++ b/arch/arm/plat-mxc/include/mach/mx25.h @@ -49,7 +49,12 @@ #define MX25_SDMA_BASE_ADDR 0x53fd4000 #define MX25_USB_BASE_ADDR 0x53ff4000 #define MX25_USB_OTG_BASE_ADDR (MX25_USB_BASE_ADDR + 0x0000) -#define MX25_USB_HS_BASE_ADDR (MX25_USB_BASE_ADDR + 0x0200) +/* + * The reference manual (IMX25RM, Rev. 1, 06/2009) specifies an offset of 0x200 + * for the host controller. Early documentation drafts specified 0x400 and + * Freescale internal sources confirm only the latter value to work. + */ +#define MX25_USB_HS_BASE_ADDR (MX25_USB_BASE_ADDR + 0x0400) #define MX25_CSI_BASE_ADDR 0x53ff8000 #define MX25_IO_P2V(x) IMX_IO_P2V(x) -- 2.20.1