From 4b2bf4b3fc066d45870b7f33fa23dbcb9cb1a27f Mon Sep 17 00:00:00 2001 From: FUJITA Tomonori Date: Tue, 29 Jun 2010 16:32:42 +0900 Subject: [PATCH] tile: remove homegrown L1_CACHE_ALIGN macro Let's use the standard L1_CACHE_ALIGN macro instead. Signed-off-by: FUJITA Tomonori Acked-by: Chris Metcalf --- arch/tile/include/asm/cache.h | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/tile/include/asm/cache.h b/arch/tile/include/asm/cache.h index c2b7dcfe5327..ee597147e5cd 100644 --- a/arch/tile/include/asm/cache.h +++ b/arch/tile/include/asm/cache.h @@ -20,7 +20,6 @@ /* bytes per L1 data cache line */ #define L1_CACHE_SHIFT CHIP_L1D_LOG_LINE_SIZE() #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) -#define L1_CACHE_ALIGN(x) (((x)+(L1_CACHE_BYTES-1)) & -L1_CACHE_BYTES) /* bytes per L1 instruction cache line */ #define L1I_CACHE_SHIFT CHIP_L1I_LOG_LINE_SIZE() -- 2.20.1