From 48f1fc3a301d50c27c07a0fe73cd3a75d4f59552 Mon Sep 17 00:00:00 2001 From: Mika Kuoppala Date: Mon, 22 May 2017 12:02:44 +0300 Subject: [PATCH] drm/i915/g33: Improve reset reliability MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit We improved the reset reliablity on gen4 with stopping all engines before commencing reset, in commit 2c80353f3cd0 ("drm/i915/g4x: Improve gpu reset reliability") Evidence indicates that this same trick works with g33. v2: proper gen naming, comment readability (Chris) Testcase: igt/gem_busy/*-hang #blb-e6850 Cc: Ville Syrjälä Cc: Chris Wilson Cc: Tomi Sarvela Signed-off-by: Mika Kuoppala Acked-by: Chris Wilson Link: http://patchwork.freedesktop.org/patch/msgid/20170522090244.2557-1-mika.kuoppala@intel.com --- drivers/gpu/drm/i915/intel_uncore.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c index df425bf629e3..9269cae5713a 100644 --- a/drivers/gpu/drm/i915/intel_uncore.c +++ b/drivers/gpu/drm/i915/intel_uncore.c @@ -1488,6 +1488,9 @@ static int g33_do_reset(struct drm_i915_private *dev_priv, unsigned engine_mask) { struct pci_dev *pdev = dev_priv->drm.pdev; + /* Stop engines before we reset; see g4x_do_reset() below for why. */ + gen3_stop_rings(dev_priv); + pci_write_config_byte(pdev, I915_GDRST, GRDOM_RESET_ENABLE); return wait_for(g4x_reset_complete(pdev), 500); } -- 2.20.1