From 480e9150ea329fc774f943a56c8de9cc361efef1 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Mon, 27 Mar 2017 14:40:36 -0400 Subject: [PATCH] drm/amdgpu/soc15: drop support for reading some registers MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit The RB harvest registers are not necessary, the driver already exposes this info via the info ioctl. GB_BACKEND_MAP has been deprecated since SI and is not relevant to the RB mapping. Reviewed-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/soc15.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c index c839994d82d0..238fcc3fa78d 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc15.c +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c @@ -300,9 +300,6 @@ static struct amdgpu_allowed_register_entry soc15_allowed_read_registers[] = { { SOC15_REG_OFFSET(GC, 0, mmCP_CPC_STALLED_STAT1), false}, { SOC15_REG_OFFSET(GC, 0, mmCP_CPC_STATUS), false}, { SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG), false}, - { SOC15_REG_OFFSET(GC, 0, mmCC_RB_BACKEND_DISABLE), false, true}, - { SOC15_REG_OFFSET(GC, 0, mmGC_USER_RB_BACKEND_DISABLE), false, true}, - { SOC15_REG_OFFSET(GC, 0, mmGB_BACKEND_MAP), false, false}, }; static uint32_t soc15_read_indexed_register(struct amdgpu_device *adev, u32 se_num, -- 2.20.1