From 472095a025cb0f4737654130e66a42806934d0f8 Mon Sep 17 00:00:00 2001 From: Donghyeok Choe Date: Mon, 16 Jul 2018 14:40:06 +0900 Subject: [PATCH] [9610] arm64: dtsi: add coresight entry Change-Id: Ie6761967ce0f0a48b3b27ca0eaff03bd5de7a598 Signed-off-by: Donghyeok Choe --- .../boot/dts/exynos/exynos9610-debug.dtsi | 38 +++++++++++++++++++ 1 file changed, 38 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/exynos9610-debug.dtsi b/arch/arm64/boot/dts/exynos/exynos9610-debug.dtsi index 5fc1c3bd17f3..6a7813581e12 100644 --- a/arch/arm64/boot/dts/exynos/exynos9610-debug.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos9610-debug.dtsi @@ -41,4 +41,42 @@ exynos-helper { compatible = "samsung,exynos-helper"; }; + + coresight@16000000 { + compatible = "exynos,coresight"; + base = <0x16000000>; + sj-offset = <0x6000>; + cl0_cpu0@400000 { + device_type = "cs"; + dbg-offset = <0x410000>; + }; + cl0_cpu1@500000 { + device_type = "cs"; + dbg-offset = <0x510000>; + }; + cl0_cpu2@600000 { + device_type = "cs"; + dbg-offset = <0x610000>; + }; + cl0_cpu3@700000 { + device_type = "cs"; + dbg-offset = <0x710000>; + }; + cl1_cpu0@800000 { + device_type = "cs"; + dbg-offset = <0x810000>; + }; + cl1_cpu1@900000 { + device_type = "cs"; + dbg-offset = <0x910000>; + }; + cl1_cpu2@a00000 { + device_type = "cs"; + dbg-offset = <0xa10000>; + }; + cl1_cpu3@b00000 { + device_type = "cs"; + dbg-offset = <0xb10000>; + }; + }; }; -- 2.20.1