From 4022e4f25b89cc64e4d07caa4d19daa5c6dc447b Mon Sep 17 00:00:00 2001 From: Rex Zhu Date: Sat, 27 May 2017 17:54:08 +0800 Subject: [PATCH] drm/amd/powerplay: enable ulv feature by default for vega10. Signed-off-by: Rex Zhu Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher --- .../drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 33 ++++++++++++++++--- 1 file changed, 28 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c index fd52f07c1fe1..2082e49ce6ae 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c @@ -126,6 +126,9 @@ static void vega10_set_default_registry_data(struct pp_hwmgr *hwmgr) data->registry_data.clock_stretcher_support = hwmgr->feature_mask & PP_CLOCK_STRETCH_MASK ? false : true; + data->registry_data.ulv_support = + hwmgr->feature_mask & PP_ULV_MASK ? true : false; + data->registry_data.disable_water_mark = 0; data->registry_data.fan_control_support = 1; @@ -2580,6 +2583,22 @@ static int vega10_enable_ulv(struct pp_hwmgr *hwmgr) return 0; } +static int vega10_disable_ulv(struct pp_hwmgr *hwmgr) +{ + struct vega10_hwmgr *data = + (struct vega10_hwmgr *)(hwmgr->backend); + + if (data->registry_data.ulv_support) { + PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr->smumgr, + false, data->smu_features[GNLD_ULV].smu_feature_bitmap), + "disable ULV Feature Failed!", + return -EINVAL); + data->smu_features[GNLD_ULV].enabled = false; + } + + return 0; +} + static int vega10_enable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr) { struct vega10_hwmgr *data = @@ -2747,11 +2766,6 @@ static int vega10_enable_dpm_tasks(struct pp_hwmgr *hwmgr) "Failed to enable VR hot feature!", result = tmp_result); - tmp_result = vega10_enable_ulv(hwmgr); - PP_ASSERT_WITH_CODE(!tmp_result, - "Failed to enable ULV!", - result = tmp_result); - tmp_result = vega10_enable_deep_sleep_master_switch(hwmgr); PP_ASSERT_WITH_CODE(!tmp_result, "Failed to enable deep sleep master switch!", @@ -2771,6 +2785,11 @@ static int vega10_enable_dpm_tasks(struct pp_hwmgr *hwmgr) "Failed to power control set level!", result = tmp_result); + tmp_result = vega10_enable_ulv(hwmgr); + PP_ASSERT_WITH_CODE(!tmp_result, + "Failed to enable ULV!", + result = tmp_result); + return result; } @@ -4532,6 +4551,10 @@ static int vega10_disable_dpm_tasks(struct pp_hwmgr *hwmgr) PP_ASSERT_WITH_CODE((tmp_result == 0), "Failed to stop DPM!", result = tmp_result); + tmp_result = vega10_disable_ulv(hwmgr); + PP_ASSERT_WITH_CODE((tmp_result == 0), + "Failed to disable ulv!", result = tmp_result); + return result; } -- 2.20.1