From 3827d10ed4278323b75bf25d09c146c050519254 Mon Sep 17 00:00:00 2001 From: Ondrej Zary Date: Tue, 1 Mar 2011 19:18:27 +0000 Subject: [PATCH] s3fb: fix 15/16bpp modes with over 115MHz pixclocks on 86C365 Trio3D Enable pixel multiplexing in 15/16bpp modes when pixclock is over 115MHz on Trio3D (86C365) cards to fix artifacts on the left side of screen. Signed-off-by: Ondrej Zary Acked-by: Ondrej Zajicek Signed-off-by: Paul Mundt --- drivers/video/s3fb.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/drivers/video/s3fb.c b/drivers/video/s3fb.c index be12145681f6..7b8fdc6d9d55 100644 --- a/drivers/video/s3fb.c +++ b/drivers/video/s3fb.c @@ -675,6 +675,15 @@ static int s3fb_set_par(struct fb_info *info) svga_wcrt_mask(par->state.vgabase, 0x67, 0x20, 0xF0); else svga_wcrt_mask(par->state.vgabase, 0x67, 0x30, 0xF0); + } else if (par->chip == CHIP_365_TRIO3D) { + svga_wcrt_mask(par->state.vgabase, 0x50, 0x10, 0x30); + if (info->var.pixclock > 8695) { + svga_wcrt_mask(par->state.vgabase, 0x67, 0x30, 0xF0); + hmul = 2; + } else { + svga_wcrt_mask(par->state.vgabase, 0x67, 0x20, 0xF0); + multiplex = 1; + } } else { svga_wcrt_mask(par->state.vgabase, 0x50, 0x10, 0x30); svga_wcrt_mask(par->state.vgabase, 0x67, 0x30, 0xF0); @@ -691,6 +700,15 @@ static int s3fb_set_par(struct fb_info *info) svga_wcrt_mask(par->state.vgabase, 0x67, 0x40, 0xF0); else svga_wcrt_mask(par->state.vgabase, 0x67, 0x50, 0xF0); + } else if (par->chip == CHIP_365_TRIO3D) { + svga_wcrt_mask(par->state.vgabase, 0x50, 0x10, 0x30); + if (info->var.pixclock > 8695) { + svga_wcrt_mask(par->state.vgabase, 0x67, 0x50, 0xF0); + hmul = 2; + } else { + svga_wcrt_mask(par->state.vgabase, 0x67, 0x40, 0xF0); + multiplex = 1; + } } else { svga_wcrt_mask(par->state.vgabase, 0x50, 0x10, 0x30); svga_wcrt_mask(par->state.vgabase, 0x67, 0x50, 0xF0); -- 2.20.1