From 33fb8698839b3a0b8685442674278626f09a9e28 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Thu, 23 Mar 2017 12:41:59 -0400 Subject: [PATCH] drm/amdgpu/gfx9: reduce the functon params for mpq setup MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit Everything we need is in the ring structure. No need to pass all the bits explicitly. Reviewed-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 30 +++++++++++++-------------- 1 file changed, 14 insertions(+), 16 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c index f46eb293cb17..74c762d78f69 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c @@ -1891,12 +1891,11 @@ static void gfx_v9_0_map_queue_enable(struct amdgpu_ring *kiq_ring, udelay(50); } -static int gfx_v9_0_mqd_init(struct amdgpu_device *adev, +static int gfx_v9_0_mqd_init(struct amdgpu_ring *ring, struct v9_mqd *mqd, - uint64_t mqd_gpu_addr, - uint64_t eop_gpu_addr, - struct amdgpu_ring *ring) + uint64_t eop_gpu_addr) { + struct amdgpu_device *adev = ring->adev; uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; uint32_t tmp; @@ -1946,8 +1945,8 @@ static int gfx_v9_0_mqd_init(struct amdgpu_device *adev, mqd->cp_hqd_pq_wptr_hi = 0; /* set the pointer to the MQD */ - mqd->cp_mqd_base_addr_lo = mqd_gpu_addr & 0xfffffffc; - mqd->cp_mqd_base_addr_hi = upper_32_bits(mqd_gpu_addr); + mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc; + mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr); /* set MQD vmid to 0 */ tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_MQD_CONTROL)); @@ -2019,10 +2018,10 @@ static int gfx_v9_0_mqd_init(struct amdgpu_device *adev, return 0; } -static int gfx_v9_0_kiq_init_register(struct amdgpu_device *adev, - struct v9_mqd *mqd, - struct amdgpu_ring *ring) +static int gfx_v9_0_kiq_init_register(struct amdgpu_ring *ring, + struct v9_mqd *mqd) { + struct amdgpu_device *adev = ring->adev; uint32_t tmp; int j; @@ -2131,8 +2130,7 @@ static int gfx_v9_0_kiq_init_register(struct amdgpu_device *adev, } static int gfx_v9_0_kiq_init_queue(struct amdgpu_ring *ring, - struct v9_mqd *mqd, - u64 mqd_gpu_addr) + struct v9_mqd *mqd) { struct amdgpu_device *adev = ring->adev; struct amdgpu_kiq *kiq = &adev->gfx.kiq; @@ -2153,9 +2151,9 @@ static int gfx_v9_0_kiq_init_queue(struct amdgpu_ring *ring, memset((void *)mqd, 0, sizeof(*mqd)); mutex_lock(&adev->srbm_mutex); soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); - gfx_v9_0_mqd_init(adev, mqd, mqd_gpu_addr, eop_gpu_addr, ring); + gfx_v9_0_mqd_init(ring, mqd, eop_gpu_addr); if (is_kiq) - gfx_v9_0_kiq_init_register(adev, mqd, ring); + gfx_v9_0_kiq_init_register(ring, mqd); soc15_grbm_select(adev, 0, 0, 0, 0); mutex_unlock(&adev->srbm_mutex); @@ -2168,7 +2166,7 @@ static int gfx_v9_0_kiq_init_queue(struct amdgpu_ring *ring, if (is_kiq) { mutex_lock(&adev->srbm_mutex); soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); - gfx_v9_0_kiq_init_register(adev, mqd, ring); + gfx_v9_0_kiq_init_register(ring, mqd); soc15_grbm_select(adev, 0, 0, 0, 0); mutex_unlock(&adev->srbm_mutex); } @@ -2197,7 +2195,7 @@ static int gfx_v9_0_kiq_resume(struct amdgpu_device *adev) r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); if (!r) { - r = gfx_v9_0_kiq_init_queue(ring, ring->mqd_ptr, ring->mqd_gpu_addr); + r = gfx_v9_0_kiq_init_queue(ring, ring->mqd_ptr); amdgpu_bo_kunmap(ring->mqd_obj); ring->mqd_ptr = NULL; } @@ -2213,7 +2211,7 @@ static int gfx_v9_0_kiq_resume(struct amdgpu_device *adev) goto done; r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); if (!r) { - r = gfx_v9_0_kiq_init_queue(ring, ring->mqd_ptr, ring->mqd_gpu_addr); + r = gfx_v9_0_kiq_init_queue(ring, ring->mqd_ptr); amdgpu_bo_kunmap(ring->mqd_obj); ring->mqd_ptr = NULL; } -- 2.20.1