From 3092d3b8e56e09ff74d7ef9f1c34a4c358e9f0fe Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 18 Feb 2016 15:16:02 +0100 Subject: [PATCH] clk: shmobile: div6: Fix .recalc_rate() using a stale divisor cpg_div6_clock_set_rate() only programs the new divisor if the clock isn't stopped. If the clock is stopped, it will update the cached divisor value only, which will be programmed into the clock registers when enabling the clock later. However, cpg_div6_clock_recalc_rate() reads the divisor from the clock registers instead of using the cached value, leading to an incorrect result if the clock is currently stopped. Make cpg_div6_clock_recalc_rate() use the cached value to fix this. Reported-by: Ramesh Shanmugasundaram Suggested-by: Laurent Pinchart Signed-off-by: Geert Uytterhoeven Reviewed-by: Laurent Pinchart Tested-by: Ramesh Shanmugasundaram --- drivers/clk/shmobile/clk-div6.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/clk/shmobile/clk-div6.c b/drivers/clk/shmobile/clk-div6.c index 999994769450..0627860233cb 100644 --- a/drivers/clk/shmobile/clk-div6.c +++ b/drivers/clk/shmobile/clk-div6.c @@ -82,9 +82,8 @@ static unsigned long cpg_div6_clock_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { struct div6_clock *clock = to_div6_clock(hw); - unsigned int div = (clk_readl(clock->reg) & CPG_DIV6_DIV_MASK) + 1; - return parent_rate / div; + return parent_rate / clock->div; } static unsigned int cpg_div6_clock_calc_div(unsigned long rate, -- 2.20.1