From 24c3ebef1ab6d5620eaaa51f69223118cac97db6 Mon Sep 17 00:00:00 2001 From: Peter De Schrijver Date: Tue, 28 Feb 2017 16:37:22 +0200 Subject: [PATCH] clk: tegra: Add aclk This clock clocks the ADSP Cortex-A9. Signed-off-by: Peter De Schrijver Reviewed-by: Mikko Perttunen Tested-by: Mikko Perttunen Signed-off-by: Thierry Reding --- drivers/clk/tegra/clk-tegra210.c | 10 ++++++++++ include/dt-bindings/clock/tegra210-car.h | 2 ++ 2 files changed, 12 insertions(+) diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c index cfe70781e2b4..9a2512a6b419 100644 --- a/drivers/clk/tegra/clk-tegra210.c +++ b/drivers/clk/tegra/clk-tegra210.c @@ -2308,6 +2308,11 @@ static struct tegra_audio_clk_info tegra210_audio_plls[] = { static struct clk **clks; +static const char * const aclk_parents[] = { + "pll_a1", "pll_c", "pll_p", "pll_a_out0", "pll_c2", "pll_c3", + "clk_m" +}; + static __init void tegra210_periph_clk_init(void __iomem *clk_base, void __iomem *pmc_base) { @@ -2369,6 +2374,11 @@ static __init void tegra210_periph_clk_init(void __iomem *clk_base, clk_register_clkdev(clk, "cml1", NULL); clks[TEGRA210_CLK_CML1] = clk; + clk = tegra_clk_register_super_clk("aclk", aclk_parents, + ARRAY_SIZE(aclk_parents), 0, clk_base + 0x6e0, + 0, NULL); + clks[TEGRA210_CLK_ACLK] = clk; + tegra_periph_clk_init(clk_base, pmc_base, tegra210_clks, &pll_p_params); } diff --git a/include/dt-bindings/clock/tegra210-car.h b/include/dt-bindings/clock/tegra210-car.h index 5aa10278ea1b..8744b19cca3e 100644 --- a/include/dt-bindings/clock/tegra210-car.h +++ b/include/dt-bindings/clock/tegra210-car.h @@ -396,6 +396,8 @@ #define TEGRA210_CLK_PLL_C_UD 364 #define TEGRA210_CLK_SCLK_MUX 365 +#define TEGRA210_CLK_ACLK 370 + #define TEGRA210_CLK_DMIC1_SYNC_CLK 388 #define TEGRA210_CLK_DMIC1_SYNC_CLK_MUX 389 #define TEGRA210_CLK_DMIC2_SYNC_CLK 390 -- 2.20.1