From 22c0d7e36f74352f7b80679003bf7edf85736b2b Mon Sep 17 00:00:00 2001 From: Beniamino Galvani Date: Mon, 24 Mar 2014 23:36:01 +0100 Subject: [PATCH] pinctrl: rockchip: fix offset of mux registers for rk3188 The correct value of .mux_offset for rk3188 seems to be 0x60 instead of 0x68. Heiko adds: GPIO0 only has the second two IOMUX registers: - GRF_GPIO0C_IOMUX at 0x68 - GRF_GPIO0D_IOMUX at 0x6c which I guess is where my mistake comes from. It looks like there does no iomux register exist at all for the first 16 pins. In any case, the current number is wrong, and the 0x60 offset is the correct one, but I guess we need to determine what the affected pins do - do they always have a gpio mux or such? Signed-off-by: Beniamino Galvani Reviewed-by: Heiko Stuebner Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-rockchip.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c index 46dddc159286..23e8812d3115 100644 --- a/drivers/pinctrl/pinctrl-rockchip.c +++ b/drivers/pinctrl/pinctrl-rockchip.c @@ -1534,7 +1534,7 @@ static struct rockchip_pin_ctrl rk3188_pin_ctrl = { .nr_banks = ARRAY_SIZE(rk3188_pin_banks), .label = "RK3188-GPIO", .type = RK3188, - .mux_offset = 0x68, + .mux_offset = 0x60, .pull_calc_reg = rk3188_calc_pull_reg_and_bit, }; -- 2.20.1