From 21461775f3d173dedec27a0402d426ba422d80a1 Mon Sep 17 00:00:00 2001 From: Tomasz Nowicki Date: Tue, 26 May 2015 20:49:15 +0800 Subject: [PATCH] x86/PCI: Clarify AMD Fam10h config access restrictions comment Clarify the comment about AMD Fam10h config access restrictions, fix typos, and add a reference to the specification. [bhelgaas: streamline] Signed-off-by: Tomasz Nowicki Signed-off-by: Hanjun Guo Signed-off-by: Bjorn Helgaas Tested-by: Suravee Suthikulpanit --- arch/x86/include/asm/pci_x86.h | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/x86/include/asm/pci_x86.h b/arch/x86/include/asm/pci_x86.h index fa1195dae425..46873fbd44e1 100644 --- a/arch/x86/include/asm/pci_x86.h +++ b/arch/x86/include/asm/pci_x86.h @@ -151,11 +151,11 @@ extern struct list_head pci_mmcfg_list; #define PCI_MMCFG_BUS_OFFSET(bus) ((bus) << 20) /* - * AMD Fam10h CPUs are buggy, and cannot access MMIO config space - * on their northbrige except through the * %eax register. As such, you MUST - * NOT use normal IOMEM accesses, you need to only use the magic mmio-config - * accessor functions. - * In fact just use pci_config_*, nothing else please. + * On AMD Fam10h CPUs, all PCI MMIO configuration space accesses must use + * %eax. No other source or target registers may be used. The following + * mmio_config_* accessors enforce this. See "BIOS and Kernel Developer's + * Guide (BKDG) For AMD Family 10h Processors", rev. 3.48, sec 2.11.1, + * "MMIO Configuration Coding Requirements". */ static inline unsigned char mmio_config_readb(void __iomem *pos) { -- 2.20.1